公开(公告)号：US06958718B2

公开(公告)日：2005-10-25

申请号：US10889217

申请日：2004-07-13

申请人： Dominic Hugo Symes ,  Simon Ford ,  Andrew Christopher Rose

发明人： Dominic Hugo Symes ,  Simon Ford ,  Andrew Christopher Rose

IPC分类号： G06F9/38 ,  G06F7/00 ,  G06F9/00 ,  G06F9/30 ,  G06F9/305 ,  G06F9/312 ,  G06F9/318 ,  G06F9/35 ,  G06F9/355 ,  H03M7/00

CPC分类号： G06F9/3004 ,  G06F9/30181 ,  G06F9/342 ,  G06F9/383

摘要： A table lookup extension instruction is provided in which index values stored within an index register D2 are used to select data elements stored within one or more table registers D0, D1 for storage into corresponding positions within a result register D3. Out-of-range index values result in the corresponding locations within the result register being left unchanged U. In this way, an offset can be applied to index values held and then those index values reused with the table registers D0, D1 being reloaded with a different portion of a table so as to give the effect of a larger table than can be directly supported by the number of table registers available.

公开(公告)号：US07219214B2

公开(公告)日：2007-05-15

申请号：US10889318

申请日：2004-07-13

申请人： Simon Andrew Ford ,  Dominic Hugo Symes ,  Andrew Christopher Rose ,  David Raymond Lutz ,  Christopher Neal Hinds

发明人： Simon Andrew Ford ,  Dominic Hugo Symes ,  Andrew Christopher Rose ,  David Raymond Lutz ,  Christopher Neal Hinds

IPC分类号： G06F9/00 ,  G06F9/44

CPC分类号： G06F9/3887 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30138 ,  G06F9/3822 ,  G06F9/3885

摘要： A data processing apparatus and method are provided for moving data between registers and memory. The data processing apparatus comprises a register data store having a plurality of registers operable to store data elements. A processor is operable to perform in parallel a data processing operation on multiple data elements occupying different lanes of parallel processing in at least one of the registers. Access logic is provided which is responsive to a single access instruction to move a plurality of data elements between a chosen one of the lanes in specified registers and a structure within memory having a structure format, the structure format having a plurality of components. The single access instruction identifies the number of components in the structure format, and the access logic is operation to arrange the plurality of data elements as they are moved such that data elements of different components are stored in different specified registers within the chosen lane whilst in memory the data elements are stored as the structure.

摘要翻译： 提供了一种用于在寄存器和存储器之间移动数据的数据处理装置和方法。 数据处理装置包括具有可操作以存储数据元素的多个寄存器的寄存器数据存储器。 处理器可操作以并行地执行对至少一个寄存器中的并行处理的不同通道的多个数据元素的数据处理操作。 提供了访问逻辑，其响应于单个访问指令，以在指定寄存器中的所选择的一个通道中移动多个数据元素，以及在具有结构格式的存储器内的结构，所述结构格式具有多个组件。 单个访问指令标识结构格式中的组件的数量，并且访问逻辑是在移动多个数据元素时排列多个数据元素的操作，使得不同组件的数据元素存储在所选择的通道内的不同指定的寄存器中，同时 存储数据元素作为结构存储。

公开(公告)号：US07210023B2

公开(公告)日：2007-04-24

申请号：US10889470

申请日：2004-07-13

申请人： Andrew Christopher Rose ,  Simon Andrew Ford ,  Dominic Hugo Symes ,  David James Seal

发明人： Andrew Christopher Rose ,  Simon Andrew Ford ,  Dominic Hugo Symes ,  David James Seal

IPC分类号： G06F7/00

CPC分类号： G06F9/3004 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30116 ,  G06F9/30138 ,  G06F9/30181 ,  G06F9/3816

摘要： The present invention provides a data processing apparatus and method for performing aligned access operations. The data processing apparatus comprises a register data store having a plurality of registers operable to store data elements, and a processor operable to perform a data processing operation on one or more data elements accessed in at least one of the registers. Further, access logic is provided which is operable in response to an access instruction to perform an access operation in order to move a number of data elements between specified registers and a portion of a memory, the portion having a start address specified by the access instruction. Further, the access instruction has an alignment specifier associated therewith which is settable either to a first value or one of a plurality of second values. The first value indicates that the start address is to be treated as byte aligned, and each of the second values indicates a different predetermined alignment that the start address is to be treated as conforming to. The access logic is then operable to adapt the access operation in dependence on the value of alignment specifier. This provides significantly improved flexibility in the performance of access operations.

摘要翻译： 本发明提供一种用于执行对准访问操作的数据处理装置和方法。 数据处理装置包括具有可操作以存储数据元素的多个寄存器的寄存器数据存储器，以及可操作以对在至少一个寄存器中访问的一个或多个数据元素执行数据处理操作的处理器。 此外，提供访问逻辑，其可响应于访问指令而操作以执行访问操作，以便在指定的寄存器和存储器的一部分之间移动多个数据元素，该部分具有由访问指令指定的起始地址 。 此外，访问指令具有与其相关联的对齐说明符，其可设置为第一值或多个第二值中的一个。 第一个值表示起始地址被视为字节对齐，并且每个第二个值指示起始地址被视为符合的不同的预定对齐方式。 然后，访问逻辑可操作以根据对准说明符的值来适应访问操作。 这样可以显着提高访问操作性能的灵活性。

公开(公告)号：US07219215B2

公开(公告)日：2007-05-15

申请号：US10889367

申请日：2004-07-13

申请人： Simon Andrew Ford ,  Dominic Hugo Symes ,  Andrew Christopher Rose ,  David Raymond Lutz ,  Christopher Neal Hinds

发明人： Simon Andrew Ford ,  Dominic Hugo Symes ,  Andrew Christopher Rose ,  David Raymond Lutz ,  Christopher Neal Hinds

IPC分类号： G06F9/40

CPC分类号： G06F9/30167 ,  G06F9/30025 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30145

摘要： A data processing apparatus and method are provided for moving data between registers and memory. The data processing apparatus comprises a register data store having a plurality of registers operable to store data elements. A processor is operable to perform in parallel a data processing operation on multiple data elements accessed in at least one of the registers. Access logic is operable in response to a single access instruction to move a plurality of data elements between specified registers and a continuous block of memory in which data elements are stored as an array of structures having a structure format, the structure format having a plurality of components. The single access instruction identifies the number of components in the structure format, and the access logic is further operable to rearrange the plurality of data elements as they are moved such that each specified register stores data elements of one component whilst in memory the data elements are stored as the array of structures.

摘要翻译： 提供了一种用于在寄存器和存储器之间移动数据的数据处理装置和方法。 数据处理装置包括具有可操作以存储数据元素的多个寄存器的寄存器数据存储器。 处理器可操作以对在至少一个寄存器中访问的多个数据元素并行地执行数据处理操作。 访问逻辑可操作以响应于单个访问指令来移动指定寄存器之间的多个数据元素和其中数据元素被存储为具有结构格式的结构的阵列的连续存储块，所述结构格式具有多个 组件。 单个访问指令标识结构格式的组件的数量，并且访问逻辑还可用于在移动多个数据元素时重新排列多个数据元素，使得每个指定的寄存器存储一个组件的数据元素，而在存储器中数据元素是 存储为结构数组。

公开(公告)号：US09223677B2

公开(公告)日：2015-12-29

申请号：US12155926

申请日：2008-06-11

申请人： Andrew Brookfield Swaine ,  Michael John Williams ,  David Kevin Hart ,  Andrew Christopher Rose

发明人： Andrew Brookfield Swaine ,  Michael John Williams ,  David Kevin Hart ,  Andrew Christopher Rose

IPC分类号： G06F11/34 ,  G06F11/36

CPC分类号： G06F11/348 ,  G06F11/3636

摘要： A data processing apparatus is provided having a plurality of processing circuits each having access to a memory. Tracing circuitry is provided for generating a stream of trace data for generating a stream of trace data corresponding to at least one of the plurality of processing circuits. Selection circuitry is provided to enable selective switching of the tracing circuitry from generating a first trace data stream corresponding to a first one of the plurality of processing circuits generating a second different trace data stream corresponding to a different one of the plurality of processing circuits. The selective switching is performed in dependence upon processing state information associating with one or more of the plurality of processing circuits. A corresponding method and computer program product are also provided.

公开(公告)号：US08621336B2

公开(公告)日：2013-12-31

申请号：US12222085

申请日：2008-08-01

申请人： Simon John Craske ,  Andrew Christopher Rose ,  Paul Stanley Hughes ,  Antony John Penton ,  Richard York ,  Simon Andrew Ford ,  Stuart David Biles ,  Alex James Waugh

发明人： Simon John Craske ,  Andrew Christopher Rose ,  Paul Stanley Hughes ,  Antony John Penton ,  Richard York ,  Simon Andrew Ford ,  Stuart David Biles ,  Alex James Waugh

IPC分类号： G06F11/00

CPC分类号： G06F11/1064

摘要： A data processing apparatus is provided comprising processing circuitry for performing data processing operations, a set associative storage device for storing data values for access by the processing circuitry when performing data processing operations, error detection circuitry for performing, for each access to the storage device, an error detection operation on the data value accessed, and maintenance circuitry associated with the storage device for performing one or more maintenance operations. The processing circuitry is arranged to issue an error detection maintenance request to the maintenance circuitry specifying at least one specific physical location within the storage device, and the maintenance circuitry is responsive to the error detection maintenance request to perform at least one dummy access to the at least one specific physical location within the storage device and to provide the processing circuitry with error status information derived from the error detection operation performed by the error detection circuitry in respect of said at least one dummy access.

公开(公告)号：US20100250802A1

公开(公告)日：2010-09-30

申请号：US12382939

申请日：2009-03-26

申请人： Alex James Waugh ,  Andrew Christopher Rose

发明人： Alex James Waugh ,  Andrew Christopher Rose

IPC分类号： G06F13/00 ,  G06F12/00

CPC分类号： G06F13/4022

摘要： A data processing apparatus and method are provided for performing hazard detection in respect of a series of access requests issued by processing circuitry for handling by one or more slave devices. The series of access requests include one or more write access requests, each write access request specifying a write operation to be performed by an addressed slave device, and each issued write access request being a pending write access request until the write operation has been completed by the addressed slave device. Hazard detection circuitry comprises a pending write access history storage having at least one buffer and at least one counter for keeping a record of each pending write access request. Update circuitry is responsive to receipt of a write access request to be issued by the processing circuitry, to perform an update process to identify that write access request as a pending write access request in one of the buffers, and if the identity of another pending write access request is overwritten by that update process, to increment a count value in one of the counters. On completion of each write access request by the addressed slave device, the update circuitry performs a further update process to remove the record of that completed write access request from the pending write access history storage. Hazard checking circuitry is then responsive to at least a subset of the access requests to be issued by the processing circuitry, to reference the pending write access history storage in order to determine whether a hazard condition occurs. The manner in which the update circuitry uses a combination of buffers and counters to keep a record of each pending write access request provides improved performance with respect to known prior art techniques, without the hardware cost that would be associated with increasing the number of buffers.

摘要翻译： 提供了一种数据处理装置和方法，用于对由一个或多个从设备处理的处理电路发出的一系列访问请求进行危险检测。 一系列访问请求包括一个或多个写访问请求，每个写访问请求指定要由寻址的从设备执行的写操作，并且每个发出的写访问请求是待处理写访问请求，直到写操作已经被 寻址的从设备。 危险检测电路包括具有至少一个缓冲器和至少一个用于保持每个未决写入访问请求的记录的计数器的待决写入访问历史存储器。 更新电路响应于由处理电路发出的写入访问请求的接收，以执行更新处理以将该写入访问请求识别为缓冲器之一中的待决写入访问请求，并且如果另一待处理写入的标识 访问请求被该更新过程覆盖，以增加其中一个计数器中的计数值。 在由所寻址的从设备完成每次写入访问请求后，更新电路执行进一步的更新处理，以从挂起的写入访问历史存储中移除该完成的写访问请求的记录。 危害检查电路然后对由处理电路发出的访问请求的至少一个子集作出响应，以引用待处理写入访问历史存储，以便确定是否发生危险状况。 更新电路使用缓冲器和计数器的组合来保持每个待处理写入访问请求的记录的方式提供了关于已知的现有技术的改进的性能，而没有与增加缓冲器数量相关联的硬件成本。

公开(公告)号：US20090164727A1

公开(公告)日：2009-06-25

申请号：US12004476

申请日：2007-12-21

申请人： Antony John Penton ,  Alex James Waugh ,  Andrew Christopher Rose ,  Paul Stanley Hughes

发明人： Antony John Penton ,  Alex James Waugh ,  Andrew Christopher Rose ,  Paul Stanley Hughes

IPC分类号： G06F12/00

CPC分类号： G06F12/0864 ,  G06F11/1064 ,  G11C15/00 ,  G11C29/42 ,  G11C29/76 ,  G11C2029/0409 ,  G11C2029/0411

摘要： A data processing apparatus and method are provided for handling hard errors occurring in a cache of the data processing apparatus. The cache storage comprising data storage having a plurality of cache lines for storing data values, and address storage having a plurality of entries, with each entry identifying for an associated cache line an address indication value, and each entry having associated error data. In response to an access request, a lookup procedure is performed to determine with reference to the address indication value held in at least one entry of the address storage whether a hit condition exists in one of the cache lines. Further, error detection circuitry determines with reference to the error data associated with the at least one entry of the address storage whether an error condition exists for that entry. Additionally, cache location avoid storage is provided having at least one record, with each record being used to store a cache line identifier identifying a specific cache line. On detection of the error condition, one of the records in the cache location avoid storage is allocated to store the cache line identifier for the specific cache line associated with the entry for which the error condition was detected. Further, the error detection circuitry causes a clean and invalidate operation to be performed in respect of the specific cache line, and the access request is then re-performed. The cache access circuitry is arranged to exclude any specific cache line identified in the cache location avoid storage from the lookup procedure. This mechanism provides a very simple and effective mechanism for handling hard errors that manifest themselves within a cache during use, so as to ensure correct operation of the cache in the presence of such hard errors. Further, the technique can be employed not only in association with write through caches but also write back caches, thus providing a very flexible solution.

公开(公告)号：US20080040592A1

公开(公告)日：2008-02-14

申请号：US11501920

申请日：2006-08-10

申请人： Vladimir Vasekin ,  Stuart David Biles ,  Andrew Christopher Rose ,  Wilco Dijkstra

发明人： Vladimir Vasekin ,  Stuart David Biles ,  Andrew Christopher Rose ,  Wilco Dijkstra

IPC分类号： G06F15/00

CPC分类号： G06F12/0875 ,  G06F9/30058 ,  G06F9/30181 ,  G06F9/3806 ,  G06F12/0862 ,  G06F2212/6028 ,  Y02D10/13

摘要： A data processing system includes an instruction fetching circuit 2, an instruction queue 4 and further processing circuits 6. A branch target cache, which maybe a branch target address cache 8, a branch target instruction cache 10 or both, is used to store branch target addresses or blocks of instructions starting at the branch target respectively. A control circuit 12 is responsive to the contents of the instruction queue 4 when a branch instruction is encountered to determine whether or not storage resources within the branch target cache 8, 10 should be allocated to that branch instruction. Storage resources within the branch target cache 8, 10 will be allocated when the number of program instructions within the instruction queue is below a threshold number and/or the estimated execution time of the program instructions is below a threshold time.

摘要翻译： 数据处理系统包括指令提取电路2，指令队列4和其他处理电路6。 分支目标高速缓存（分支目标地址高速缓存8，分支目标指令高速缓存10或两者）分别用于存储从分支目标开始的分支目标地址或指令块。 当遇到分支指令时，控制电路12响应于指令队列4的内容，以确定分支目标高速缓存8,10中的存储资源是否应被分配给该分支指令。 当指令队列内的程序指令数量低于阈值数量和/或程序指令的估计执行时间低于阈值时间时，将分配分支目标缓存器8,10内的存储资源。

公开(公告)号：US07000094B2

公开(公告)日：2006-02-14

申请号：US09887560

申请日：2001-06-25

申请人： Edward Colles Nevill ,  Andrew Christopher Rose

发明人： Edward Colles Nevill ,  Andrew Christopher Rose

IPC分类号： G06F9/30

CPC分类号： G06F9/4843 ,  G06F9/30 ,  G06F9/30134 ,  G06F9/30149 ,  G06F9/30174 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3853 ,  G06F9/3861

摘要： A data processing apparatus includes a processor core having a bank of registers. The bank of registers include a set of registers that are used for the storage of stack operands. Instructions from a second instruction set specifying stack operands are translated by an instruction translator into instructions of a first instruction set (or control signals corresponding to those instructions) specifying register operands. These translated instructions are then executed by the processor core. The instruction translator has multiple mapping states for controlling which registers corresponding to which stack operands within the stack. Changes between mapping states are carried out in dependence of stack operands being added to or removed from the set of registers.

摘要翻译： 数据处理装置包括具有一组寄存器的处理器核心。 寄存器组包括一组用于存储堆栈操作数的寄存器。 来自指定栈操作数的第二指令集的指令由指令转换器转换成指定寄存器操作数的第一指令集（或对应于那些指令的控制信号）的指令。 这些翻译的指令然后由处理器核心执行。 指令转换器具有多个映射状态，用于控制对应于栈内哪个堆栈操作数的寄存器。 映射状态之间的变化是根据添加到寄存器组中或从该组寄存器中移除的堆栈操作数进行的。