公开(公告)号：US5132613A

公开(公告)日：1992-07-21

申请号：US620973

申请日：1990-11-30

申请人： Donald J. Papae ,  Donald F. Schomaker ,  Michael A. Sorna

发明人： Donald J. Papae ,  Donald F. Schomaker ,  Michael A. Sorna

IPC分类号： G01R1/073 ,  G01R31/26 ,  G01R31/28 ,  H01L21/66

CPC分类号： G01R31/2884

摘要： An integrated circuit test structure is comprised of a stacked substrate MLC space transformer (5). A top surface of an interface substrate (12) is employed for decoupling capacitor (36) placement. The top surface has metal conductors (20) exposed thereon for terminating power supply buses from a tester (1). Individual layers of a personalization substrate (14) are fabricated to redundantly extend internal power plane metalization (22) to the sidewalls. Redundant pads (26) are placed on each personalization layer to increase the surface area for side mount contact. Metal pads (18) are deposited over the exposed sidewall metal for forming a sidewall contact to the power planes within the personalization substrate. The personalization substrate is joined to the upper surface of the interface substrate and the sidewall contacts are conductively coupled by conductive members (40) to the interface substrate metal conductors (20), thereby providing a low inductance, low resistance DC path from the tester to a device under test (4). The decoupling capacitors are electrically coupled to the metal lines in close proximity the personalization substrate thereby minimizing the associated lead inductance and maximizing the effectiveness of the decoupling capacitors.

摘要翻译： 集成电路测试结构由层叠衬底MLC空间变压器（5）组成。 接口衬底（12）的顶表面用于去耦电容器（36）放置。 顶面具有暴露在其上的金属导体（20），用于从测试器（1）端接电源总线。 制造个性化衬底（14）的各个层以将内部功率平面金属化（22）冗余地扩展到侧壁。 冗余垫（26）放置在每个个性化层上以增加用于侧装接触的表面积。 金属焊盘（18）沉积在暴露的侧壁金属上，以形成与个性化衬底内的电源平面的侧壁接触。 个性化衬底连接到界面衬底的上表面，并且侧壁触点通过导电构件（40）导电耦合到界面衬底金属导体（20），从而提供从测试仪到低电阻的低电阻，低电阻DC路径 被测设备（4）。 去耦电容器紧邻个性化衬底电耦合到金属线，从而最小化相关的引线电感并最大限度地提高去耦电容器的有效性。

公开(公告)号：US5144228A

公开(公告)日：1992-09-01

申请号：US690404

申请日：1991-04-23

申请人： Michael A. Sorna ,  Donald J. Papae

发明人： Michael A. Sorna ,  Donald J. Papae

IPC分类号： G01R1/073

CPC分类号： G01R1/07321

摘要： A probe interface assembly connects a set of signal lines and a set of power lines from a circuit tester to one integrated circuit (IC) chip disposed among multiple circuit chips on a semiconductor wafer. The assembly includes a plurality of electrically conductive planes including metal mesh and conductive strips which are spaced apart by ceramic planes contiguous the conductive planes. The signal lines and the power lines enter the assembly with relatively large spacing at an input plane facing the tester, and exit the assembly with relatively small spacing at an output plane facing the chip. Within the assembly, each power line branches into a plurality of conducting vias for reducing resistance and inductance of the power lines. Connection of the vias to the power lines is accomplished by conductive planes near the output plane. Other ones of the conductive planes, near the input plane, interconnect input and output signal lines. Ground planes are interposed between power planes and signal planes.

摘要翻译： 探针接口组件将一组信号线和一组电源线从电路测试器连接到设置在半导体晶片上的多个电路芯片之间的一个集成电路（IC）芯片。 组件包括多个导电平面，包括金属网和导电条，导电条由与导电平面相邻的陶瓷平面隔开。 信号线和电源线在面向测试器的输入平面处以相对大的间隔进入组件，并且在面向芯片的输出平面处以相对较小的间隔离开组件。 在组件内，每个电源线分支成多个导电通孔，用于降低电力线的电阻和电感。 通孔与电源线的连接由输出平面附近的导电平面实现。 在输入平面附近的其他导电平面互连输入和输出信号线。 接地层插在电源层和信号面之间。

公开(公告)号：US08618839B2

公开(公告)日：2013-12-31

申请号：US13418961

申请日：2012-03-13

申请人： Howard H. Chi ,  Haitao O. Dai ,  Kai D. Feng ,  Donald J. Papae

发明人： Howard H. Chi ,  Haitao O. Dai ,  Kai D. Feng ,  Donald J. Papae

IPC分类号： G01R19/00

CPC分类号： H03F3/45183 ,  H03F3/45609 ,  H03F3/68 ,  H03F2200/408 ,  H03F2200/78

摘要： Embodiments of the present invention provide an approach for utilizing a sense amplifier to select a suitable circuit, wherein a suitable circuit generates a voltage that is greater than or equal to a configurable reference voltage. An amplifier gain selector selects a voltage gain of a sense amplifier having input terminals, auxiliary inputs, an output, an array of resistive loads, and the amplifier gain selector. Auxiliary inputs are utilized to nullify direct current (DC) offset voltage of the sense amplifier. Combinatorial logic circuitry connects the input terminals of the sense amplifier to output terminals of a circuit that is within a group of circuits. A comparator circuit determines if the circuit generates a voltage greater than or equal to a configurable reference voltage, based on the output of the sense amplifier.

摘要翻译： 本发明的实施例提供了一种利用读出放大器来选择合适电路的方法，其中合适的电路产生大于或等于可配置参考电压的电压。 放大器增益选择器选择具有输入端，辅助输入，输出，电阻性负载阵列和放大器增益选择器的读出放大器的电压增益。 辅助输入用于消除读出放大器的直流（DC）偏移电压。 组合逻辑电路将读出放大器的输入端连接到一组电路内的电路的输出端。 比较器电路基于读出放大器的输出来确定电路是否产生大于或等于可配置参考电压的电压。

公开(公告)号：US20140035670A1

公开(公告)日：2014-02-06

申请号：US13566805

申请日：2012-08-03

申请人： Howard H. Chi ,  Haitao O. Dai ,  Kai D. Feng ,  Donald J. Papae

发明人： Howard H. Chi ,  Haitao O. Dai ,  Kai D. Feng ,  Donald J. Papae

IPC分类号： H03F3/45

CPC分类号： G06F7/588 ,  G09C1/00 ,  H04L9/0866 ,  H04L9/3278 ,  H04L2209/12

摘要： A FET pair based physically unclonable function (PUF) circuit with a constant common mode voltage and methods of use are disclosed. The circuit includes a first n-type field effect transistor (NFET) and a second NFET. The circuit also includes a first load resistor coupled to the first NFET by a first p-type field effect transistor (PFET) and a second load resistor coupled to the second NFET by a second PFET. The circuit further comprises a closed loop, wherein the closed loop creates a constant common mode voltage.

摘要翻译： 公开了一种具有恒定共模电压的物理不可克隆功能（PUF）电路和使用方法的FET对。 电路包括第一n型场效应晶体管（NFET）和第二NFET。 电路还包括通过第一p型场效应晶体管（PFET）耦合到第一NFET的第一负载电阻器和通过第二PFET耦合到第二NFET的第二负载电阻器。 电路还包括闭环，其中闭环产生恒定的共模电压。

公开(公告)号：US20130241652A1

公开(公告)日：2013-09-19

申请号：US13418961

申请日：2012-03-13

申请人： Howard H. Chi ,  Haitao O. Dai ,  Kai D. Feng ,  Donald J. Papae

发明人： Howard H. Chi ,  Haitao O. Dai ,  Kai D. Feng ,  Donald J. Papae

IPC分类号： H03F3/45

CPC分类号： H03F3/45183 ,  H03F3/45609 ,  H03F3/68 ,  H03F2200/408 ,  H03F2200/78

摘要： Embodiments of the present invention provide an approach for utilizing a sense amplifier to select a suitable circuit, wherein a suitable circuit generates a voltage that is greater than or equal to a configurable reference voltage. An amplifier gain selector selects a voltage gain of a sense amplifier having input terminals, auxiliary inputs, an output, an array of resistive loads, and the amplifier gain selector. Auxiliary inputs are utilized to nullify direct current (DC) offset voltage of the sense amplifier. Combinatorial logic circuitry connects the input terminals of the sense amplifier to output terminals of a circuit that is within a group of circuits. A comparator circuit determines if the circuit generates a voltage greater than or equal to a configurable reference voltage, based on the output of the sense amplifier.

摘要翻译： 本发明的实施例提供了一种利用读出放大器来选择合适电路的方法，其中合适的电路产生大于或等于可配置参考电压的电压。 放大器增益选择器选择具有输入端，辅助输入，输出，电阻性负载阵列和放大器增益选择器的读出放大器的电压增益。 辅助输入用于消除读出放大器的直流（DC）偏移电压。 组合逻辑电路将读出放大器的输入端连接到一组电路内的电路的输出端。 比较器电路基于读出放大器的输出来确定电路是否产生大于或等于可配置参考电压的电压。

公开(公告)号：US20090179323A1

公开(公告)日：2009-07-16

申请号：US12013653

申请日：2008-01-14

申请人： Kai Di Feng ,  Alvin Jose Joseph ,  Donald J. Papae ,  Xiaojin Wei

发明人： Kai Di Feng ,  Alvin Jose Joseph ,  Donald J. Papae ,  Xiaojin Wei

IPC分类号： H01L23/38 ,  H01L21/60

CPC分类号： H01L23/3677 ,  H01L23/38 ,  H01L24/48 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A system and method in which a semiconductor chip has electrically inactive metal-filled vias adjacent to a semiconductor device or devices to be cooled and the semiconductor device or devices are preferably surrounded by thermally insulating vias. The metal-filled vias are contacted with a thermoelectric cooler to remove excess heat from the semiconductor device or devices.

摘要翻译： 一种系统和方法，其中半导体芯片具有与半导体器件或待冷却的器件相邻的电惰性金属填充的通孔，并且半导体器件或器件优选地被隔热通孔包围。 金属填充的通孔与热电冷却器接触以从半导体器件或器件去除多余的热量。

公开(公告)号：US08941405B2

公开(公告)日：2015-01-27

申请号：US13566805

申请日：2012-08-03

申请人： Howard H. Chi ,  Haitao O. Dai ,  Kai D. Feng ,  Donald J. Papae

发明人： Howard H. Chi ,  Haitao O. Dai ,  Kai D. Feng ,  Donald J. Papae

IPC分类号： H03K19/00 ,  H05K3/00

CPC分类号： G06F7/588 ,  G09C1/00 ,  H04L9/0866 ,  H04L9/3278 ,  H04L2209/12

摘要： A FET pair based physically unclonable function (PUF) circuit with a constant common mode voltage and methods of use are disclosed. The circuit includes a first n-type field effect transistor (NFET) and a second NFET. The circuit also includes a first load resistor coupled to the first NFET by a first p-type field effect transistor (PFET) and a second load resistor coupled to the second NFET by a second PFET. The circuit further comprises a closed loop, wherein the closed loop creates a constant common mode voltage.

摘要翻译： 公开了一种具有恒定共模电压的物理不可克隆功能（PUF）电路和使用方法的FET对。 电路包括第一n型场效应晶体管（NFET）和第二NFET。 电路还包括通过第一p型场效应晶体管（PFET）耦合到第一NFET的第一负载电阻器和通过第二PFET耦合到第二NFET的第二负载电阻器。 电路还包括闭环，其中闭环产生恒定的共模电压。

公开(公告)号：US07759789B2

公开(公告)日：2010-07-20

申请号：US12013653

申请日：2008-01-14

申请人： Kai Di Feng ,  Alvin Jose Joseph ,  Donald J. Papae ,  Xiaojin Wei

发明人： Kai Di Feng ,  Alvin Jose Joseph ,  Donald J. Papae ,  Xiaojin Wei

IPC分类号： H01L23/38 ,  H01L21/60

CPC分类号： H01L23/3677 ,  H01L23/38 ,  H01L24/48 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A system and method in which a semiconductor chip has electrically inactive metal-filled vias adjacent to a semiconductor device or devices to be cooled and the semiconductor device or devices are preferably surrounded by thermally insulating vias. The metal-filled vias are contacted with a thermoelectric cooler to remove excess heat from the semiconductor device or devices.

摘要翻译： 一种系统和方法，其中半导体芯片具有与半导体器件或待冷却的器件相邻的电惰性金属填充的通孔，并且半导体器件或器件优选地被隔热通孔包围。 金属填充的通孔与热电冷却器接触以从半导体器件或器件去除多余的热量。

公开(公告)号：US06965171B1

公开(公告)日：2005-11-15

申请号：US10709931

申请日：2004-06-07

申请人： Tim H. Lee ,  Chon C. Lei ,  Donald J. Papae ,  Francis F. Szenher

发明人： Tim H. Lee ,  Chon C. Lei ,  Donald J. Papae ,  Francis F. Szenher

IPC分类号： H01L23/02 ,  H01L23/367 ,  G01L23/48 ,  G01L23/52 ,  G01L29/40

CPC分类号： H01L23/3675 ,  H01L23/3677 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/3011

摘要： An integrated circuit (IC) chip module includes at least one integrated circuit chip mounted upon a substrate, and a plurality of passive components mounted upon the substrate. A polymer based bib has at least one opening formed therein, the at least one opening configured to accommodate the at least one integrated circuit chip therein, and the bib further configured for attachment to one or more of the plurality of passive components. A protective cap is mounted over the at least one integrated circuit chip and attached to the substrate, wherein the bib is configured to retain thereon a thermally conductive paste initially applied to at least one of the integrated circuit chip and the protective cap.

摘要翻译： 集成电路（IC）芯片模块包括安装在基板上的至少一个集成电路芯片和安装在基板上的多个无源部件。 基于聚合物的围兜具有形成在其中的至少一个开口，所述至少一个开口被配置为在其中容纳所述至少一个集成电路芯片，并且所述围兜还被配置为附接到所述多个无源元件中的一个或多个。 保护盖安装在所述至少一个集成电路芯片上并附接到所述基板，其中所述围拢被配置为在其上保持最初施加到所述集成电路芯片和所述保护盖中的至少一个的导热浆。