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    MEMORY DEVICE EMPLOYING OPEN BIT LINE ARCHITECTURE FOR PROVIDING IDENTICAL DATA TOPOLOGY ON REPAIRED MEMORY CELL BLOCK AND METHOD THEREOF
    1.
    发明申请
    MEMORY DEVICE EMPLOYING OPEN BIT LINE ARCHITECTURE FOR PROVIDING IDENTICAL DATA TOPOLOGY ON REPAIRED MEMORY CELL BLOCK AND METHOD THEREOF 失效
    使用开放位线架构的记忆装置，用于在修复的记忆体块上提供标识数据拓扑及其方法

    公开(公告)号：US20060028900A1

    公开(公告)日：2006-02-09

    申请号：US11197227

    申请日：2005-08-04

    申请人： Dong-Hak Shin ,  Ho-Sung Song ,  Byung-Sik Moon

    发明人： Dong-Hak Shin ,  Ho-Sung Song ,  Byung-Sik Moon

    IPC分类号： G11C8/00 ,  G11C7/06 ,  G11C29/00

    CPC分类号： G11C7/18 ,  G11C29/808 ,  G11C29/846

    摘要： A memory device has at least one pair of memory cell blocks, a spare row decoder, a data exchange control signal generator and a data exchange unit. When a defective memory cell in a first memory cell block is repaired with a spare memory cell in a second memory cell block that neighbors (or is adjacent) the first memory cell block, the data topology of the memory cell of the first memory cell may be matched to the memory cell of the second memory cell block.

    摘要翻译： 存储器件具有至少一对存储单元块，备用行解码器，数据交换控制信号发生器和数据交换单元。 当第一存储器单元块中的有缺陷的存储器单元用邻近（或相邻）第一存储器单元块的第二存储器单元块中的备用存储器单元修复时，第一存储器单元的存储单元的数据拓扑可以 与第二存储单元块的存储单元匹配。

    Memory device employing open bit line architecture for providing identical data topology on repaired memory cell block and method thereof
    2.
    发明授权
    Memory device employing open bit line architecture for providing identical data topology on repaired memory cell block and method thereof 失效
    采用开放位线架构以在修复的存储单元块上提供相同数据拓扑的存储器件及其方法

    公开(公告)号：US07027339B2

    公开(公告)日：2006-04-11

    申请号：US11197227

    申请日：2005-08-04

    申请人： Dong-Hak Shin ,  Ho-Sung Song ,  Byung-Sik Moon

    发明人： Dong-Hak Shin ,  Ho-Sung Song ,  Byung-Sik Moon

    IPC分类号： G11C7/00

    CPC分类号： G11C7/18 ,  G11C29/808 ,  G11C29/846

    摘要： A memory device has at least one pair of memory cell blocks, a spare row decoder, a data exchange control signal generator and a data exchange unit. When a defective memory cell in a first memory cell block is repaired with a spare memory cell in a second memory cell block that neighbors (or is adjacent) the first memory cell block, the data topology of the memory cell of the first memory cell may be matched to the memory cell of the second memory cell block.

    摘要翻译： 存储器件具有至少一对存储单元块，备用行解码器，数据交换控制信号发生器和数据交换单元。 当第一存储器单元块中的有缺陷的存储器单元用邻近（或相邻）第一存储器单元块的第二存储器单元块中的备用存储器单元修复时，第一存储器单元的存储单元的数据拓扑可以 与第二存储单元块的存储单元匹配。

    Semiconductor memory devices having signal delay controller and methods performed therein
    3.
    发明授权
    Semiconductor memory devices having signal delay controller and methods performed therein 失效
    具有信号延迟控制器的半导体存储器件及其中执行的方法

    公开(公告)号：US07599234B2

    公开(公告)日：2009-10-06

    申请号：US11349995

    申请日：2006-02-09

    申请人： Jeong-Sik Nam ,  Ho-Sung Song

    发明人： Jeong-Sik Nam ,  Ho-Sung Song

    IPC分类号： G11C11/063

    CPC分类号： G11C5/063 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08

    摘要： A semiconductor memory device may have a memory cell array with respective memory cells disposed at intersections of rows and columns. The semiconductor memory device may also include at least one decoder and at least one delay controller. The decoder may select a row or column of the memory cell. The signal delay controller may control a delay of an activation signal applied to the row or column by the at least one decoder based on at least one of a position of the at least one memory cell associated with the selected row or column and a line loading capacitance value of the selected memory cell.

    摘要翻译： 半导体存储器件可以具有存储单元阵列，其中相应的存储单元设置在行和列的相交处。 半导体存储器件还可以包括至少一个解码器和至少一个延迟控制器。 解码器可以选择存储器单元的行或列。 信号延迟控制器可以基于与所选择的行或列相关联的至少一个存储器单元的位置和行负载中的至少一个来控​​制由至少一个解码器施加到行或列的激活信号的延迟 所选存储单元的电容值。

    Dynamic random access memory device and &mgr;BGA package using multiple reference voltage pads
    4.
    发明授权
    Dynamic random access memory device and &mgr;BGA package using multiple reference voltage pads 有权
    动态随机存取存储器件和muBGA封装使用多个参考电压焊盘

    公开(公告)号：US06310796B1

    公开(公告)日：2001-10-30

    申请号：US09631062

    申请日：2000-08-01

    申请人： Ho-Sung Song

    发明人： Ho-Sung Song

    IPC分类号： G11C506

    CPC分类号： G11C7/1084 ,  G11C7/1078 ,  G11C11/4096

    摘要： A dynamic random access memory device and a &mgr;BGA package for the device use multiple pads for a reference voltage. The device includes n input receivers, n data input pads, and x reference voltage pads. Each input receiver operates synchronously with a clock signal and includes a differential amplifying unit that generates an output data signal according to a voltage difference between an input data signal and a reference voltage. The n data input pads respectively connect to the n input receivers and transfer the input data signals to the input receivers. The n input receivers are divided into x groups according to their positions, and the x reference voltage input pads respectively connect to the x groups of input receivers for commonly applying the reference voltage to the input receivers in the respective groups. Each reference voltage input pad can connect to its group of input receivers through one or multiple common lines. The package includes a first ball that receives the reference voltage. The first ball is commonly connected to the x reference voltage input pads of the device. The average and maximum distances between the reference voltage input pads and input receivers are much shorter with multiple reference voltage pads. Accordingly, the noise level of the reference voltage is smaller, thereby improving a margin in data setup and hold times of the input receivers and the operational reliability of products. Filters connected to the reference voltage pads can further reduce the noise in the reference voltage at the input receivers.

    摘要翻译： 动态随机存取存储器件和器件的muBGA封装使用多个焊盘作为参考电压。 该器件包括n个输入接收器，n个数据输入焊盘和x个参考电压焊盘。 每个输入接收器与时钟信号同步工作，并且包括差分放大单元，其根据输入数据信号和参考电压之间的电压差产生输出数据信号。 n个数据输入焊盘分别连接到n个输入接收器，并将输入数据信号传送到输入接收器。 n个输入接收器根据它们的位置被分成x组，并且x参考电压输入焊盘分别连接到x组输入接收器，以通常将参考电压施加到相应组中的输入接收器。 每个参考电压输入板可以通过一条或多条公共线连接到其组输入接收器。 该包装包括接收参考电压的第一球。 第一个球通常连接到设备的x参考电压输入焊盘。 多个参考电压焊盘，参考电压输入焊盘和输入接收器之间的平均和最大距离要短得多。 因此，参考电压的噪声电平较小，从而提高了输入接收机的数据建立和保持时间以及产品的操作可靠性。 连接到参考电压焊盘的滤波器可以进一步降低输入接收器处参考电压的噪声。

    Semiconductor memory devices having signal delay controller and methods performed therein
    5.
    发明申请
    Semiconductor memory devices having signal delay controller and methods performed therein 失效
    具有信号延迟控制器的半导体存储器件及其中执行的方法

    公开(公告)号：US20100014366A1

    公开(公告)日：2010-01-21

    申请号：US12585636

    申请日：2009-09-21

    申请人： Jeong-Sik Nam ,  Ho-Sung Song

    发明人： Jeong-Sik Nam ,  Ho-Sung Song

    IPC分类号： G11C7/00 ,  G11C8/00

    CPC分类号： G11C5/063 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08

    摘要： A semiconductor memory device may have a memory cell array with respective memory cells disposed at intersections of rows and columns. The semiconductor memory device may also include at least one decoder and at least one delay controller. The decoder may select a row or column of the memory cell. The signal delay controller may control a delay of an activation signal applied to the row or column by the at least one decoder based on at least one of a position of the at least one memory cell associated with the selected row or column and a line loading capacitance value of the selected memory cell.

    摘要翻译： 半导体存储器件可以具有存储单元阵列，其中相应的存储单元设置在行和列的相交处。 半导体存储器件还可以包括至少一个解码器和至少一个延迟控制器。 解码器可以选择存储器单元的行或列。 信号延迟控制器可以基于与所选择的行或列相关联的至少一个存储器单元的位置和行负载中的至少一个来控​​制由至少一个解码器施加到行或列的激活信号的延迟 所选存储单元的电容值。

    Semiconductor memory devices having signal delay controller and methods performed therein
    6.
    发明授权
    Semiconductor memory devices having signal delay controller and methods performed therein 失效
    具有信号延迟控制器的半导体存储器件及其中执行的方法

    公开(公告)号：US08027219B2

    公开(公告)日：2011-09-27

    申请号：US12585636

    申请日：2009-09-21

    申请人： Jeong-Sik Nam ,  Ho-Sung Song

    发明人： Jeong-Sik Nam ,  Ho-Sung Song

    IPC分类号： G11C8/00

    CPC分类号： G11C5/063 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08

    摘要： A semiconductor memory device may have a memory cell array with respective memory cells disposed at intersections of rows and columns. The semiconductor memory device may also include at least one decoder and at least one delay controller. The decoder may select a row or column of the memory cell. The signal delay controller may control a delay of an activation signal applied to the row or column by the at least one decoder based on at least one of a position of the at least one memory cell associated with the selected row or column and a line loading capacitance value of the selected memory cell.

    摘要翻译： 半导体存储器件可以具有存储单元阵列，其中相应的存储单元设置在行和列的相交处。 半导体存储器件还可以包括至少一个解码器和至少一个延迟控制器。 解码器可以选择存储器单元的行或列。 信号延迟控制器可以基于与所选择的行或列相关联的至少一个存储器单元的位置和行负载中的至少一个来控​​制由至少一个解码器施加到行或列的激活信号的延迟 所选存储单元的电容值。

    Semiconductor memory device capable of selecting a plurality of refresh cycle modes
    7.
    发明授权
    Semiconductor memory device capable of selecting a plurality of refresh cycle modes 失效
    能够选择多个刷新周期模式的半导体存储器件

    公开(公告)号：US6115311A

    公开(公告)日：2000-09-05

    申请号：US979

    申请日：1997-12-30

    申请人： Ho-Sung Song ,  Jong-Hyun Choi ,  Jun-Young Jyun

    发明人： Ho-Sung Song ,  Jong-Hyun Choi ,  Jun-Young Jyun

    IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C11/406 ,  G11C7/00

    CPC分类号： G11C11/406 ,  G11C7/1045

    摘要： A semiconductor memory device having an improved column select control circuit. The semiconductor memory device includes a memory cell array consisting of a plurality of volatile memory cells and a column select line decoder for selecting a column line of the memory cell array. The semiconductor memory device includes at least two different refresh cycle modes designed within a single chip. A mode select circuit generates a mode select signal for selecting one of at least two refresh modes. A column select control circuit controls the enable time of the column select line decoder enable signal responsive to the mode select signal and to row address strobe signal for providing the column select line decoder enable signal to the column select line decoder.

    摘要翻译： 一种具有改进的列选择控制电路的半导体存储器件。 半导体存储器件包括由多个易失性存储器单元组成的存储单元阵列和用于选择存储单元阵列的列线的列选择线解码器。 半导体存储器件包括在单个芯片内设计的至少两种不同的刷新周期模式。 模式选择电路产生用于选择至少两种刷新模式之一的模式选择信号。 列选择控制电路响应于模式选择信号控制列选择线解码器使能信号的使能时间和行地址选通信号，以向列选择行解码器提供列选择线解码器使能信号。

    Address converter semiconductor device and semiconductor memory device having the same
    8.
    发明授权
    Address converter semiconductor device and semiconductor memory device having the same 失效
    地址转换器半导体器件及其半导体存储器件

    公开(公告)号：US07319634B2

    公开(公告)日：2008-01-15

    申请号：US11501905

    申请日：2006-08-08

    申请人： Chul-Hwan Choo ,  Ho-Sung Song

    发明人： Chul-Hwan Choo ,  Ho-Sung Song

    IPC分类号： G11C8/00

    CPC分类号： G11C8/18 ,  G11C7/04 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4082 ,  G11C29/18

    摘要： An address converter of a semiconductor device comprises a clock generating portion for generating at least one clock signal when a power voltage is applied; a control signal setting means for setting a control signal during a mode setting operation; a polarity selecting signal generating portion for generating at least one polarity selecting signal in response to the at least one clock signal and the control signal; and an address converting portion for converting at least one bit of an address applied from an external portion to output a converted address in response to the at least one polarity selecting signal.

    摘要翻译： 半导体器件的地址转换器包括时钟产生部分，用于在施加电源电压时产生至少一个时钟信号; 控制信号设定装置，用于在模式设定操作期间设定控制信号; 极性选择信号产生部分，用于响应于至少一个时钟信号和控制信号产生至少一个极性选择信号; 以及地址转换部分，用于转换从外部部分施加的地址的至少一位，以响应于所述至少一个极性选择信号输出转换的地址。

    Address converter semiconductor device and semiconductor memory device having the same
    9.
    发明申请
    Address converter semiconductor device and semiconductor memory device having the same 失效
    地址转换器半导体器件及其半导体存储器件

    公开(公告)号：US20070153619A1

    公开(公告)日：2007-07-05

    申请号：US11501905

    申请日：2006-08-08

    申请人： Chul-Hwan Choo ,  Ho-Sung Song

    发明人： Chul-Hwan Choo ,  Ho-Sung Song

    IPC分类号： G11C8/00

    CPC分类号： G11C8/18 ,  G11C7/04 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4082 ,  G11C29/18

    摘要： An address converter of a semiconductor device comprises a clock generating portion for generating at least one clock signal when a power voltage is applied; a control signal setting means for setting a control signal during a mode setting operation; a polarity selecting signal generating portion for generating at least one polarity selecting signal in response to the at least one clock signal and the control signal; and an address converting portion for converting at least one bit of an address applied from an external portion to output a converted address in response to the at least one polarity selecting signal.

    摘要翻译： 半导体器件的地址转换器包括时钟产生部分，用于在施加电源电压时产生至少一个时钟信号; 控制信号设定装置，用于在模式设定操作期间设定控制信号; 极性选择信号产生部分，用于响应于至少一个时钟信号和控制信号产生至少一个极性选择信号; 以及地址转换部分，用于转换从外部部分施加的地址的至少一位，以响应于所述至少一个极性选择信号输出转换的地址。