公开(公告)号：US20070165455A1

公开(公告)日：2007-07-19

申请号：US11637686

申请日：2006-12-12

申请人： Jae-Kwan Park ,  Ki-Nam Kim ,  Soon-Moon Jung

发明人： Jae-Kwan Park ,  Ki-Nam Kim ,  Soon-Moon Jung

IPC分类号： G11C16/04 ,  H01L21/336 ,  H01L29/788

CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11568 ,  H01L27/11578

摘要： A NAND-type nonvolatile memory device includes a semiconductor substrate and a first ground selection line and a first string selection line disposed on the substrate in parallel to each other. A plurality of parallel first word lines are interposed on the substrate between the first ground selection line and the first string selection line. A first impurity-doped region is formed in the semiconductor substrate adjacent to the first word lines, the first ground selection line, and the first string selection line. A first interlayer dielectric layer is disposed on the first ground selection line, the first string selection line, the plurality of first word lines, and the semiconductor substrate. An epitaxial contact plug contacts the semiconductor substrate through the first interlayer dielectric layer. A single crystalline semiconductor layer is disposed on the first interlayer dielectric layer that contacts the epitaxial contact plug. A plurality of parallel second word lines is disposed on the single crystalline semiconductor layer. A second impurity-doped region formed in the single crystalline semiconductor layer adjacent to the second word lines. A second interlayer dielectric layer is disposed on the plurality of second word lines and the single crystalline semiconductor layer.

摘要翻译： NAND型非易失性存储器件包括半导体衬底和彼此平行地布置在衬底上的第一接地选择线和第一串选择线。 在第一接地选择线和第一串选择线之间的基板上插入多个平行的第一字线。 在与第一字线，第一地选择线和第一串选择线相邻的半导体衬底中形成第一杂质掺杂区。 第一层间介电层设置在第一接地选择线，第一串选择线，多个第一字线和半导体衬底上。 外延接触插塞通过第一层间介电层与半导体衬底接触。 单晶半导体层设置在与外延接触插塞接触的第一层间电介质层上。 多个平行的第二字线布置在单晶半导体层上。 形成在与第二字线相邻的单晶半导体层中的第二杂质掺杂区。 第二层间介电层设置在多个第二字线和单晶半导体层上。

公开(公告)号：US07626228B2

公开(公告)日：2009-12-01

申请号：US11637686

申请日：2006-12-12

申请人： Jae-Kwan Park ,  Ki-Nam Kim ,  Soon-Moon Jung

发明人： Jae-Kwan Park ,  Ki-Nam Kim ,  Soon-Moon Jung

IPC分类号： H01L29/792 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11568 ,  H01L27/11578

摘要： A NAND-type nonvolatile memory device includes a semiconductor substrate and a first ground selection line and a first string selection line disposed on the substrate in parallel to each other. A plurality of parallel first word lines are interposed on the substrate between the first ground selection line and the first string selection line. A first impurity-doped region is formed in the semiconductor substrate adjacent to the first word lines, the first ground selection line, and the first string selection line. A first interlayer dielectric layer is disposed on the first ground selection line, the first string selection line, the plurality of first word lines, and the semiconductor substrate. An epitaxial contact plug contacts the semiconductor substrate through the first interlayer dielectric layer. A single crystalline semiconductor layer is disposed on the first interlayer dielectric layer that contacts the epitaxial contact plug. A plurality of parallel second word lines is disposed on the single crystalline semiconductor layer. A second impurity-doped region formed in the single crystalline semiconductor layer adjacent to the second word lines. A second interlayer dielectric layer is disposed on the plurality of second word lines and the single crystalline semiconductor layer.

摘要翻译： NAND型非易失性存储器件包括半导体衬底和彼此平行地布置在衬底上的第一接地选择线和第一串选择线。 在第一接地选择线和第一串选择线之间的基板上插入多个平行的第一字线。 在与第一字线，第一地选择线和第一串选择线相邻的半导体衬底中形成第一杂质掺杂区。 第一层间介电层设置在第一接地选择线，第一串选择线，多个第一字线和半导体衬底上。 外延接触插塞通过第一层间介电层与半导体衬底接触。 单晶半导体层设置在与外延接触插塞接触的第一层间电介质层上。 多个平行的第二字线布置在单晶半导体层上。 形成在与第二字线相邻的单晶半导体层中的第二杂质掺杂区。 第二层间介电层设置在多个第二字线和单晶半导体层上。

公开(公告)号：US08026504B2

公开(公告)日：2011-09-27

申请号：US12379814

申请日：2009-03-02

申请人： Jun-Beom Park ,  Soon-Moon Jung ,  Ki-Nam Kim

发明人： Jun-Beom Park ,  Soon-Moon Jung ,  Ki-Nam Kim

IPC分类号： H01L47/00

CPC分类号： H01L27/24 ,  Y10S977/774

摘要： A semiconductor device and a method of forming the same are provided. The method includes preparing a semiconductor substrate. Insulating layers may be sequentially formed on the semiconductor substrate. Active elements may be formed between the insulating layers. A common node may be formed in the insulating layers to be electrically connected to the active elements. The common node and the active elements may be 2-dimensionally and repeatedly arranged on the semiconductor substrate.

摘要翻译： 提供半导体器件及其形成方法。 该方法包括制备半导体衬底。 可以在半导体衬底上依次形成绝缘层。 可以在绝缘层之间形成有源元件。 可以在绝缘层中形成公共节点以电连接到有源元件。 公共节点和有源元件可以二维重复地布置在半导体衬底上。

公开(公告)号：US20100330752A1

公开(公告)日：2010-12-30

申请号：US12842703

申请日：2010-07-23

申请人： Jae-Hun Jeong ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

发明人： Jae-Hun Jeong ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

IPC分类号： H01L21/322 ,  H01L21/336

CPC分类号： H01L27/10802 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/108 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841

摘要： A one transistor DRAM device includes: a substrate with an insulating layer, a first semiconductor layer provided on the insulating layer and including a first source region and a first region which are in contact with the insulating layer and a first floating body between the first source region and the first drain region, a first gate pattern to cover the first floating body, a first interlayer dielectric to cover the first gate pattern, a second semiconductor layer provided on the first interlayer dielectric and including a second source region and a second drain region which are in contact with the first interlayer dielectric and a second floating body between the second source region and the second drain region, and a second gate pattern to cover the second floating body.

摘要翻译： 一个晶体管DRAM器件包括：具有绝缘层的衬底，设置在绝缘层上的第一半导体层，包括与绝缘层接触的第一源极区域和第一区域以及第一源极 区域和第一漏极区域，覆盖第一浮动体的第一栅极图案，覆盖第一栅极图案的第一层间电介质，设置在第一层间电介质上并包括第二源极区域和第二漏极区域的第二半导体层 其与第一层间电介质接触，第二浮动体与第二源极区和第二漏极区之间接触，第二栅极图案覆盖第二浮体。

公开(公告)号：US20090253257A1

公开(公告)日：2009-10-08

申请号：US12478538

申请日：2009-06-04

申请人： Young-Chul Jang ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

发明人： Young-Chul Jang ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

IPC分类号： H01L21/8246 ,  H01L21/4763 ,  H01L21/3205

CPC分类号： H01L27/105 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551

摘要： A nonvolatile memory device includes a semiconductor substrate having a first well region of a first conductivity type, and at least one semiconductor layer formed on the semiconductor substrate. A first cell array is formed on the semiconductor substrate, and a second cell array formed on the semiconductor layer. The semiconductor layer includes a second well region of the first conductivity type having a doping concentration greater than a doping concentration of the first well region of the first conductivity type. As the doping concentration of the second well region is increased, a resistance difference may be reduced between the first and second well regions.

摘要翻译： 非易失性存储器件包括具有第一导电类型的第一阱区和形成在半导体衬底上的至少一个半导体层的半导体衬底。 第一单元阵列形成在半导体衬底上，第二单元阵列形成在半导体层上。 半导体层包括第一导电类型的第二阱区，其具有大于第一导电类型的第一阱区的掺杂浓度的掺杂浓度。 随着第二阱区域的掺杂浓度增加，可以在第一和第二阱区域之间减小电阻差。

公开(公告)号：US20090218558A1

公开(公告)日：2009-09-03

申请号：US12379814

申请日：2009-03-02

申请人： Jun-Beom Park ,  Soon-Moon Jung ,  Ki-Nam Kim

发明人： Jun-Beom Park ,  Soon-Moon Jung ,  Ki-Nam Kim

IPC分类号： H01L47/00

CPC分类号： H01L27/24 ,  Y10S977/774

摘要： A semiconductor device and a method of forming the same are provided. The method includes preparing a semiconductor substrate. Insulating layers may be sequentially formed on the semiconductor substrate. Active elements may be formed between the insulating layers. A common node may be formed in the insulating layers to be electrically connected to the active elements. The common node and the active elements may be 2-dimensionally and repeatedly arranged on the semiconductor substrate.

摘要翻译： 提供半导体器件及其形成方法。 该方法包括制备半导体衬底。 可以在半导体衬底上依次形成绝缘层。 可以在绝缘层之间形成有源元件。 可以在绝缘层中形成公共节点以电连接到有源元件。 公共节点和有源元件可以二维重复地布置在半导体衬底上。

公开(公告)号：US20110300683A1

公开(公告)日：2011-12-08

申请号：US13137420

申请日：2011-08-15

申请人： Jun-Beom Park ,  Soon-Moon Jung ,  Ki-Nam Kim

发明人： Jun-Beom Park ,  Soon-Moon Jung ,  Ki-Nam Kim

IPC分类号： H01L45/00

CPC分类号： H01L27/24 ,  Y10S977/774

摘要： A semiconductor device and a method of forming the same are provided. The method includes preparing a semiconductor substrate. Insulating layers may be sequentially formed on the semiconductor substrate. Active elements may be formed between the insulating layers. A common node may be formed in the insulating layers to be electrically connected to the active elements. The common node and the active elements may be 2-dimensionally and repeatedly arranged on the semiconductor substrate.

公开(公告)号：US07910433B2

公开(公告)日：2011-03-22

申请号：US12478538

申请日：2009-06-04

申请人： Young-Chul Jang ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

发明人： Young-Chul Jang ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/84

CPC分类号： H01L27/105 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551

摘要： A nonvolatile memory device includes a semiconductor substrate having a first well region of a first conductivity type, and at least one semiconductor layer formed on the semiconductor substrate. A first cell array is formed on the semiconductor substrate, and a second cell array formed on the semiconductor layer. The semiconductor layer includes a second well region of the first conductivity type having a doping concentration greater than a doping concentration of the first well region of the first conductivity type. As the doping concentration of the second well region is increased, a resistance difference may be reduced between the first and second well regions.

摘要翻译： 非易失性存储器件包括具有第一导电类型的第一阱区和形成在半导体衬底上的至少一个半导体层的半导体衬底。 第一单元阵列形成在半导体衬底上，第二单元阵列形成在半导体层上。 半导体层包括第一导电类型的第二阱区，其具有大于第一导电类型的第一阱区的掺杂浓度的掺杂浓度。 随着第二阱区域的掺杂浓度增加，可以在第一和第二阱区域之间减小电阻差。

公开(公告)号：US20110163411A1

公开(公告)日：2011-07-07

申请号：US13049495

申请日：2011-03-16

申请人： Young-Chul Jang ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

发明人： Young-Chul Jang ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

IPC分类号： H01L27/08

CPC分类号： H01L27/105 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551

摘要： A nonvolatile memory device includes a semiconductor substrate having a first well region of a first conductivity type, and at least one semiconductor layer formed on the semiconductor substrate. A first cell array is formed on the semiconductor substrate, and a second cell array formed on the semiconductor layer. The semiconductor layer includes a second well region of the first conductivity type having a doping concentration greater than a doping concentration of the first well region of the first conductivity type. As the doping concentration of the second well region is increased, a resistance difference may be reduced between the first and second well regions.

摘要翻译： 非易失性存储器件包括具有第一导电类型的第一阱区和形成在半导体衬底上的至少一个半导体层的半导体衬底。 第一单元阵列形成在半导体衬底上，第二单元阵列形成在半导体层上。 半导体层包括第一导电类型的第二阱区，其具有大于第一导电类型的第一阱区的掺杂浓度的掺杂浓度。 随着第二阱区域的掺杂浓度增加，可以在第一和第二阱区域之间减小电阻差。

公开(公告)号：US20100240209A1

公开(公告)日：2010-09-23

申请号：US12792912

申请日：2010-06-03

申请人： Jae-Hun Jeong ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

发明人： Jae-Hun Jeong ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

IPC分类号： H01L21/28

CPC分类号： H01L21/26506 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/167 ,  H01L29/34 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/7883 ,  H01L29/792

摘要： Provided are semiconductor devices and methods of forming the same. The semiconductor devices include a substrate further including a hydrogen implantation layer and a gate structure formed on the hydrogen implantation layer to include a first insulating layer, a charge storage layer, a second insulating layer and a conductive layer.

摘要翻译： 提供半导体器件及其形成方法。 半导体器件包括还包括氢注入层和在氢注入层上形成的包括第一绝缘层，电荷存储层，第二绝缘层和导电层的栅极结构的衬底。