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    One transistor DRAM device and method of forming the same
    2.
    发明授权
    One transistor DRAM device and method of forming the same 有权
    一种晶体管DRAM器件及其形成方法

    公开(公告)号：US07795651B2

    公开(公告)日：2010-09-14

    申请号：US12024459

    申请日：2008-02-01

    申请人： Jae-Hun Jeong ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

    发明人： Jae-Hun Jeong ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

    IPC分类号： H01L31/112

    CPC分类号： H01L27/10802 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/108 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841

    摘要： A one transistor DRAM device includes: a substrate with an insulating layer, a first semiconductor layer provided on the insulating layer and including a first source region and a first region which are in contact with the insulating layer and a first floating body between the first source region and the first drain region, a first gate pattern to cover the first floating body, a first interlayer dielectric to cover the first gate pattern, a second semiconductor layer provided on the first interlayer dielectric and including a second source region and a second drain region which are in contact with the first interlayer dielectric and a second floating body between the second source region and the second drain region, and a second gate pattern to cover the second floating body.

    摘要翻译： 一个晶体管DRAM器件包括：具有绝缘层的衬底，设置在绝缘层上的第一半导体层，包括与绝缘层接触的第一源极区域和第一区域以及第一源极 区域和第一漏极区域，覆盖第一浮动体的第一栅极图案，覆盖第一栅极图案的第一层间电介质，设置在第一层间电介质上并包括第二源极区域和第二漏极区域的第二半导体层 其与第一层间电介质接触，第二浮动体与第二源极区和第二漏极区之间接触，第二栅极图案覆盖第二浮体。

    Methods of Forming One Transistor DRAM Devices
    3.
    发明申请
    Methods of Forming One Transistor DRAM Devices 有权
    形成一个晶体管DRAM器件的方法

    公开(公告)号：US20100330752A1

    公开(公告)日：2010-12-30

    申请号：US12842703

    申请日：2010-07-23

    申请人： Jae-Hun Jeong ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

    发明人： Jae-Hun Jeong ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

    IPC分类号： H01L21/322 ,  H01L21/336

    CPC分类号： H01L27/10802 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/108 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841

    摘要： A one transistor DRAM device includes: a substrate with an insulating layer, a first semiconductor layer provided on the insulating layer and including a first source region and a first region which are in contact with the insulating layer and a first floating body between the first source region and the first drain region, a first gate pattern to cover the first floating body, a first interlayer dielectric to cover the first gate pattern, a second semiconductor layer provided on the first interlayer dielectric and including a second source region and a second drain region which are in contact with the first interlayer dielectric and a second floating body between the second source region and the second drain region, and a second gate pattern to cover the second floating body.

    摘要翻译： 一个晶体管DRAM器件包括：具有绝缘层的衬底，设置在绝缘层上的第一半导体层，包括与绝缘层接触的第一源极区域和第一区域以及第一源极 区域和第一漏极区域，覆盖第一浮动体的第一栅极图案，覆盖第一栅极图案的第一层间电介质，设置在第一层间电介质上并包括第二源极区域和第二漏极区域的第二半导体层 其与第一层间电介质接触，第二浮动体与第二源极区和第二漏极区之间接触，第二栅极图案覆盖第二浮体。

    Methods of forming one transistor DRAM devices
    4.
    发明授权
    Methods of forming one transistor DRAM devices 有权
    形成一个晶体管DRAM器件的方法

    公开(公告)号：US08168530B2

    公开(公告)日：2012-05-01

    申请号：US12842703

    申请日：2010-07-23

    申请人： Jae-Hun Jeong ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

    发明人： Jae-Hun Jeong ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

    IPC分类号： H01L21/4763

    CPC分类号： H01L27/10802 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/108 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841

    摘要： A one transistor DRAM device includes: a substrate with an insulating layer, a first semiconductor layer provided on the insulating layer and including a first source region and a first region which are in contact with the insulating layer and a first floating body between the first source region and the first drain region, a first gate pattern to cover the first floating body, a first interlayer dielectric to cover the first gate pattern, a second semiconductor layer provided on the first interlayer dielectric and including a second source region and a second drain region which are in contact with the first interlayer dielectric and a second floating body between the second source region and the second drain region, and a second gate pattern to cover the second floating body.

    摘要翻译： 一个晶体管DRAM器件包括：具有绝缘层的衬底，设置在绝缘层上的第一半导体层，包括与绝缘层接触的第一源极区域和第一区域以及第一源极 区域和第一漏极区域，覆盖第一浮动体的第一栅极图案，覆盖第一栅极图案的第一层间电介质，设置在第一层间电介质上并包括第二源极区域和第二漏极区域的第二半导体层 其与第一层间电介质接触，第二浮动体与第二源极区和第二漏极区之间接触，第二栅极图案覆盖第二浮体。

    NAND flash memory device with 3-dimensionally arranged memory cell transistors
    5.
    发明申请
    NAND flash memory device with 3-dimensionally arranged memory cell transistors 审中-公开
    具有三维排列的存储单元晶体管的NAND闪存器件

    公开(公告)号：US20080067554A1

    公开(公告)日：2008-03-20

    申请号：US11705163

    申请日：2007-02-12

    申请人： Jae-Hun Jeong ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

    发明人： Jae-Hun Jeong ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

    IPC分类号： H01L29/76

    CPC分类号： H01L27/115 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551

    摘要： A NAND flash memory device includes a plurality of stacked semiconductor layers, device isolation layer patterns disposed in predetermined regions of each of the plurality of semiconductor layers, the device isolation layers defining active regions, source and drain impurity regions in the active regions, a source line plug structure electrically connecting the source impurity regions, and a bit-line plug structure electrically connecting the drain impurity regions, wherein the source impurity regions are electrically connected to the semiconductor layers.

    摘要翻译： NAND闪速存储器件包括多个层叠的半导体层，设置在多个半导体层中的每一个的预定区域中的器件隔离层图案，器件隔离层限定有源区域，有源区域中的源极和漏极杂质区域，源极 电连接源杂质区的线插头结构，以及电连接漏极杂质区的位线插头结构，其中源杂质区电连接到半导体层。

    METHODS OF FORMING NAND-TYPE NONVOLATILE MEMORY DEVICES
    6.
    发明申请
    METHODS OF FORMING NAND-TYPE NONVOLATILE MEMORY DEVICES 有权
    形成NAND型非易失性存储器件的方法

    公开(公告)号：US20090233405A1

    公开(公告)日：2009-09-17

    申请号：US12474896

    申请日：2009-05-29

    申请人： Hoo-Sung Cho ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jong-Hyuk Kim ,  Jae-Hun Jeong ,  Jae-Hoon Jang

    发明人： Hoo-Sung Cho ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jong-Hyuk Kim ,  Jae-Hun Jeong ,  Jae-Hoon Jang

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11524 ,  H01L27/0688 ,  H01L27/11551

    摘要： Methods of forming a NAND-type nonvolatile memory device include: forming first common drains and first common sources alternatively in an active region which is defined in a semiconductor substrate and extends one direction, forming a first insulating layer covering an entire surface of the semiconductor substrate, patterning the first insulating layer to form seed contact holes which are arranged at regular distance and expose the active region, forming a seed contact structure filling each of the seed contact holes and a semiconductor layer disposed on the first insulating layer and contacting the seed contact structures, patterning the semiconductor layer to form a semiconductor pattern which extends in the one direction and is disposed over the active region, forming second common drains and second common sources disposed alternatively in the semiconductor pattern in the one direction, forming a second insulating layer covering an entire surface of the semiconductor substrate, forming a source line pattern continuously penetrating the second insulating layer, the semiconductor pattern and the first insulating layer, the source line pattern being connected with the first and second common sources, wherein a grain boundary of the semiconductor layer is positioned at a center between the one pair of seed contact structures adjacent to each other, and is positioned over the first common drain or the first common source.

    摘要翻译： 形成NAND型非易失性存储器件的方法包括：在半导体衬底中限定的有源区域中交替形成第一公共漏极和第一公共源，并延伸一个方向，形成覆盖半导体衬底的整个表面的第一绝缘层 图案化第一绝缘层以形成以规则距离布置的暴露有源区域的种子接触孔，形成填充每个种子接触孔的种子接触结构以及设置在第一绝缘层上并接触种子接触的半导体层 结构，图案化所述半导体层以形成在所述一个方向上延伸并设置在所述有源区上方的半导体图案，形成沿所述一个方向交替设置在所述半导体图案中的第二公共漏极和第二公共源，形成第二绝缘层覆盖层 半导体衬底的整个表面 使源极线图案连续地穿过第二绝缘层，半导体图案和第一绝缘层，源极线图案与第一和第二共用源连接，其中半导体层的晶界位于第二绝缘层之间的中心 一对种子接触结构彼此相邻，并且位于第一公共漏极或第一公共源的上方。

    Nand-type non-volatile memory device
    7.
    发明授权
    Nand-type non-volatile memory device 失效
    Nand型非易失性存储器件

    公开(公告)号：US07554140B2

    公开(公告)日：2009-06-30

    申请号：US11651892

    申请日：2007-01-10

    申请人： Hoo-Sung Cho ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jong-Hyuk Kim ,  Jae-Hun Jeong ,  Jae-Hoon Jang

    发明人： Hoo-Sung Cho ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jong-Hyuk Kim ,  Jae-Hun Jeong ,  Jae-Hoon Jang

    IPC分类号： H01L31/062

    CPC分类号： H01L27/11524 ,  H01L27/0688 ,  H01L27/11551

    摘要： Provided is a NAND-type nonvolatile memory device and method of forming the same. In the method, a plurality of cell layers are stacked on a semiconductor substrate. Seed contact holes for forming a semiconductor pattern included in a stacked cell are formed at regular distance. At this time, the seed contact holes are arranged such that a bit line plug or a source line pattern is disposed at a center between one pair of seed contact holes adjacent to each other.

    摘要翻译： 提供了一种NAND型非易失性存储器件及其形成方法。 在该方法中，多个单元层层叠在半导体基板上。 用于形成包含在层叠电池中的半导体图案的种子接触孔以规则的距离形成。 此时，种子接触孔布置成使得位线插头或源极线图案设置在彼此相邻的一对种子接触孔之间的中心处。