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    NAND-type non-volatile memory devices having a stacked structure
    1.
    发明授权
    NAND-type non-volatile memory devices having a stacked structure 失效
    具有堆叠结构的NAND型非易失性存储器件

    公开(公告)号：US07626228B2

    公开(公告)日：2009-12-01

    申请号：US11637686

    申请日：2006-12-12

    申请人： Jae-Kwan Park ,  Ki-Nam Kim ,  Soon-Moon Jung

    发明人： Jae-Kwan Park ,  Ki-Nam Kim ,  Soon-Moon Jung

    IPC分类号： H01L29/792 ,  H01L23/48 ,  H01L23/52

    CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11568 ,  H01L27/11578

    摘要： A NAND-type nonvolatile memory device includes a semiconductor substrate and a first ground selection line and a first string selection line disposed on the substrate in parallel to each other. A plurality of parallel first word lines are interposed on the substrate between the first ground selection line and the first string selection line. A first impurity-doped region is formed in the semiconductor substrate adjacent to the first word lines, the first ground selection line, and the first string selection line. A first interlayer dielectric layer is disposed on the first ground selection line, the first string selection line, the plurality of first word lines, and the semiconductor substrate. An epitaxial contact plug contacts the semiconductor substrate through the first interlayer dielectric layer. A single crystalline semiconductor layer is disposed on the first interlayer dielectric layer that contacts the epitaxial contact plug. A plurality of parallel second word lines is disposed on the single crystalline semiconductor layer. A second impurity-doped region formed in the single crystalline semiconductor layer adjacent to the second word lines. A second interlayer dielectric layer is disposed on the plurality of second word lines and the single crystalline semiconductor layer.

    摘要翻译： NAND型非易失性存储器件包括半导体衬底和彼此平行地布置在衬底上的第一接地选择线和第一串选择线。 在第一接地选择线和第一串选择线之间的基板上插入多个平行的第一字线。 在与第一字线，第一地选择线和第一串选择线相邻的半导体衬底中形成第一杂质掺杂区。 第一层间介电层设置在第一接地选择线，第一串选择线，多个第一字线和半导体衬底上。 外延接触插塞通过第一层间介电层与半导体衬底接触。 单晶半导体层设置在与外延接触插塞接触的第一层间电介质层上。 多个平行的第二字线布置在单晶半导体层上。 形成在与第二字线相邻的单晶半导体层中的第二杂质掺杂区。 第二层间介电层设置在多个第二字线和单晶半导体层上。

    NAND-type non-volatile memory devices having a stacked structure and associated methods of forming and operating the same
    2.
    发明申请
    NAND-type non-volatile memory devices having a stacked structure and associated methods of forming and operating the same 失效
    具有堆叠结构的NAND型非易失性存储器件及其形成和操作的相关方法

    公开(公告)号：US20070165455A1

    公开(公告)日：2007-07-19

    申请号：US11637686

    申请日：2006-12-12

    申请人： Jae-Kwan Park ,  Ki-Nam Kim ,  Soon-Moon Jung

    发明人： Jae-Kwan Park ,  Ki-Nam Kim ,  Soon-Moon Jung

    IPC分类号： G11C16/04 ,  H01L21/336 ,  H01L29/788

    CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11568 ,  H01L27/11578

    摘要： A NAND-type nonvolatile memory device includes a semiconductor substrate and a first ground selection line and a first string selection line disposed on the substrate in parallel to each other. A plurality of parallel first word lines are interposed on the substrate between the first ground selection line and the first string selection line. A first impurity-doped region is formed in the semiconductor substrate adjacent to the first word lines, the first ground selection line, and the first string selection line. A first interlayer dielectric layer is disposed on the first ground selection line, the first string selection line, the plurality of first word lines, and the semiconductor substrate. An epitaxial contact plug contacts the semiconductor substrate through the first interlayer dielectric layer. A single crystalline semiconductor layer is disposed on the first interlayer dielectric layer that contacts the epitaxial contact plug. A plurality of parallel second word lines is disposed on the single crystalline semiconductor layer. A second impurity-doped region formed in the single crystalline semiconductor layer adjacent to the second word lines. A second interlayer dielectric layer is disposed on the plurality of second word lines and the single crystalline semiconductor layer.

    摘要翻译： NAND型非易失性存储器件包括半导体衬底和彼此平行地布置在衬底上的第一接地选择线和第一串选择线。 在第一接地选择线和第一串选择线之间的基板上插入多个平行的第一字线。 在与第一字线，第一地选择线和第一串选择线相邻的半导体衬底中形成第一杂质掺杂区。 第一层间介电层设置在第一接地选择线，第一串选择线，多个第一字线和半导体衬底上。 外延接触插塞通过第一层间介电层与半导体衬底接触。 单晶半导体层设置在与外延接触插塞接触的第一层间电介质层上。 多个平行的第二字线布置在单晶半导体层上。 形成在与第二字线相邻的单晶半导体层中的第二杂质掺杂区。 第二层间介电层设置在多个第二字线和单晶半导体层上。

    CELL STRING OF A MEMORY CELL ARRAY AND METHOD OF ERASING THE SAME
    7.
    发明申请
    CELL STRING OF A MEMORY CELL ARRAY AND METHOD OF ERASING THE SAME 审中-公开
    存储单元阵列的单元格字符串及其擦除方法

    公开(公告)号：US20110211392A1

    公开(公告)日：2011-09-01

    申请号：US12961647

    申请日：2010-12-07

    申请人： Jae-Ho Kim ,  Jae-Kwan Park ,  Byung-Jun Hwang ,  Sung-Bo Shim ,  Hye-Young Kwon

    发明人： Jae-Ho Kim ,  Jae-Kwan Park ,  Byung-Jun Hwang ,  Sung-Bo Shim ,  Hye-Young Kwon

    IPC分类号： G11C16/06 ,  H01L29/788 ,  H01L29/792 ,  G11C16/04

    CPC分类号： G11C16/16 ,  G11C16/0408 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

    摘要： A cell string included in a memory cell array of a nonvolatile memory device includes a plurality of memory cells, a string select transistor, and a ground select transistor. The plurality of memory cells are connected in series. The string select transistor is connected between a bitline and the plurality of memory cells, and has a structure substantially the same as a structure of each memory cell. The ground select transistor is connected between the plurality of memory cells and a common source line, and has a structure substantially the same as the structure of each memory cell.

    摘要翻译： 包括在非易失性存储器件的存储单元阵列中的单元串包括多个存储单元，串选择晶体管和接地选择晶体管。 多个存储单元串联连接。 串选择晶体管连接在位线和多个存储单元之间，并且具有与每个存储单元的结构基本相同的结构。 接地选择晶体管连接在多个存储单元和公共源极线之间，并且具有与每个存储单元的结构基本相同的结构。

    Semiconductor devices having a convex active region and methods of forming the same
    9.
    发明申请
    Semiconductor devices having a convex active region and methods of forming the same 有权
    具有凸起的有源区的半导体器件及其形成方法

    公开(公告)号：US20080057644A1

    公开(公告)日：2008-03-06

    申请号：US11642198

    申请日：2006-12-20

    申请人： Dong-Hwa Kwak ,  Jae-Kwan Park ,  Yong-Sik Yim ,  Won-Cheol Jeong ,  Jae-Hwang Sim

    发明人： Dong-Hwa Kwak ,  Jae-Kwan Park ,  Yong-Sik Yim ,  Won-Cheol Jeong ,  Jae-Hwang Sim

    IPC分类号： H01L21/336

    CPC分类号： H01L27/105 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/66795 ,  H01L29/7853 ,  H01L29/7854

    摘要： Methods of forming a semiconductor device include forming a trench mask pattern on a semiconductor substrate having active regions and device isolation regions. A thermal oxidation process is performed using the trench mask pattern as a diffusion mask to form a thermal oxide layer defining a convex upper surface of the active regions. The thermal oxide layer and the semiconductor substrate are etched using the trench mask pattern as an etch mask to form trenches defining convex upper surfaces of the active regions. The trench mask pattern is removed to expose the convex upper surfaces of the active regions. Gate patterns are formed extending over the active regions.

    摘要翻译： 形成半导体器件的方法包括在具有有源区和器件隔离区的半导体衬底上形成沟槽掩模图案。 使用沟槽掩模图案作为扩散掩模进行热氧化处理，以形成限定有源区的凸上表面的热氧化层。 使用沟槽掩模图案作为蚀刻掩模蚀刻热氧化物层和半导体衬底，以形成限定有源区的凸上表面的沟槽。 去除沟槽掩模图案以露出活性区域的凸上表面。 形成在有源区域上延伸的栅极图案。

    Pulse generators with variable pulse width and sense amplifiers using the same and related methods
    10.
    发明申请
    Pulse generators with variable pulse width and sense amplifiers using the same and related methods 审中-公开
    具有可变脉冲宽度的脉冲发生器和使用相同方法的读出放大器

    公开(公告)号：US20060152262A1

    公开(公告)日：2006-07-13

    申请号：US11327681

    申请日：2006-01-06

    申请人： Jae-Kwan Park

    发明人： Jae-Kwan Park

    IPC分类号： H03K3/017

    CPC分类号： H03K5/133 ,  G11C7/08 ,  H03K5/153 ,  H03K2005/00032 ,  H03K2005/00202

    摘要： Pulse generators include a delay circuit that is responsive to an input signal. The pulse generators also include an output circuit that is configured to generate an output pulse signal in response to the output of the delay circuit. In these pulse generators, the delay circuit has a variable delay that increases proportional to increases in a power supply voltage. Sense amplifiers that include these pulse generators are also provided.

    摘要翻译： 脉冲发生器包括响应于输入信号的延迟电路。 脉冲发生器还包括输出电路，其配置为响应于延迟电路的输出而产生输出脉冲信号。 在这些脉冲发生器中，延迟电路具有与电源电压增加成比例的可变延迟。 还提供了包括这些脉冲发生器的感应放大器。