中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

15 records (took 0.013 seconds)

    Semiconductor Memory Devices Including Offset Bit Lines
    3.
    发明申请
    Semiconductor Memory Devices Including Offset Bit Lines 有权
    包括偏移位线的半导体存储器件

    公开(公告)号：US20090218609A1

    公开(公告)日：2009-09-03

    申请号：US12465202

    申请日：2009-05-13

    Applicant: Doo-Hoon Goo ,  Han-Ku Cho ,  Joo-Tae Moon ,  Sang-Gyun Woo ,  Gi-Sung Yeo ,  Kyoung-Yun Baek

    Inventor： Doo-Hoon Goo ,  Han-Ku Cho ,  Joo-Tae Moon ,  Sang-Gyun Woo ,  Gi-Sung Yeo ,  Kyoung-Yun Baek

    IPC: H01L27/108

    CPC classification number: H01L27/10814 ,  H01L27/0207 ,  H01L27/10882 ,  H01L27/11502

    Abstract: A semiconductor memory device may include a substrate having a plurality of active regions wherein each active region has a length in a direction of a first axis and a width in a direction of a second axis. The length may be greater than the width, and the plurality of active regions may be provided in a plurality of columns of active regions in the direction of the second axis. A plurality of wordline pairs may be provided on the substrate, with each wordline pair crossing active regions of a respective column of active regions defining a drain portion of each active region between wordlines of the respective wordline pair. A plurality of bitlines on the substrate may cross the plurality of wordline pairs, with each bitline being electrically coupled to a respective drain portion of an active region of each column, and with each bitline being arranged between the respective drain portion and another drain portion of an adjacent active region of the same column.

    Abstract translation: 半导体存储器件可以包括具有多个有源区的衬底，其中每个有源区具有在第一轴的方向上的长度和在第二轴的方向上的宽度。 长度可以大于宽度，并且多个有源区可以在第二轴的方向上设置在多个有效区列中。 可以在衬底上提供多个字线对，其中每个字线对跨越相应的有效区域列的有源区域，在相应字线对的字线之间限定每个有效区域的漏极部分。 衬底上的多个位线可以跨过多个字线对，每个位线电耦合到每个列的有源区的相应漏极部分，并且每个位线布置在相应的漏极部分和另一个漏极部分的另一个漏极部分之间 相同列的相邻有效区域。

    Method of forming self-aligned contact pads of non-straight type semiconductor memory device
    5.
    发明申请
    Method of forming self-aligned contact pads of non-straight type semiconductor memory device 有权
    形成非直型半导体存储器件的自对准接触焊盘的方法

    公开(公告)号：US20050070080A1

    公开(公告)日：2005-03-31

    申请号：US10944151

    申请日：2004-09-16

    Applicant: Eun-Mi Lee ,  Doo-Hoon Goo ,  Jung-Hyeon Lee ,  Gi-Sung Yeo

    Inventor： Eun-Mi Lee ,  Doo-Hoon Goo ,  Jung-Hyeon Lee ,  Gi-Sung Yeo

    IPC: H01L21/28 ,  H01L21/4763 ,  H01L21/60 ,  H01L23/485

    CPC classification number: H01L21/76897 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Embodiments of the invention provide methods of forming SAC pads in non-straight semiconductor device having non-straight type or separate type active regions. A plurality of gate line structures extending in one direction may be formed on a semiconductor substrate having non-straight active regions. An interlayer insulating layer covering gate line structures may be formed on the gate line structures. Then, a photo-resist layer may be formed on the interlayer insulating layer. A photo-resist pattern may be formed through exposing and developing the photo-resist layer by using a photo-mask having, for example, a bar type, a wave type, or a reverse active type pattern. Then, contact holes exposing source/drain regions may be formed by etching the interlayer insulating layer using the photo-resist pattern as an etching mask. Contact pads may then be formed by filling the contact holes with a conductive material.

    Abstract translation: 本发明的实施例提供了在具有非直型或分离型有源区的非直线半导体器件中形成SAC焊盘的方法。 可以在具有非直线活性区域的半导体衬底上形成沿一个方向延伸的多个栅极线结构。 覆盖栅极线结构的层间绝缘层可以形成在栅极线结构上。 然后，可以在层间绝缘层上形成光致抗蚀剂层。 可以通过使用具有例如棒型，波型或反向活性型图案的光掩模，通过曝光和显影光致抗蚀剂层来形成光致抗蚀剂图案。 然后，可以通过使用光刻胶图案作为蚀刻掩模蚀刻层间绝缘层来形成暴露源极/漏极区的接触孔。 然后可以通过用导电材料填充接触孔来形成接触垫。

    Methods of forming fine patterns using a nanoimprint lithography
    6.
    发明授权
    Methods of forming fine patterns using a nanoimprint lithography 失效
    使用纳米压印光刻形成精细图案的方法

    公开(公告)号：US08287792B2

    公开(公告)日：2012-10-16

    申请号：US12657750

    申请日：2010-01-27

    Applicant: Jeong-Hoon Lee ,  Jeong-Ho Yeo ,  Joo-On Park ,  In-Sung Kim ,  Doo-Hoon Goo ,  Jin-Hong Park ,  Chang-Min Park

    Inventor： Jeong-Hoon Lee ,  Jeong-Ho Yeo ,  Joo-On Park ,  In-Sung Kim ,  Doo-Hoon Goo ,  Jin-Hong Park ,  Chang-Min Park

    IPC: B29C59/00

    CPC classification number: G03F7/0002 ,  B29C43/003 ,  B29C2043/025 ,  B82Y10/00 ,  B82Y40/00

    Abstract: In a method of forming fine patterns, a photocurable coating layer is formed on a substrate. A first surface of a template makes contact with the photocurable coating layer. The first surface of the template includes at least two first patterns having a first dispersion degree of sizes, and at least one portion of the first surface of the template includes a photo attenuation member. A light is irradiated onto the photocurable coating layer through the template to form a cured coating layer including second patterns having a second dispersion degree of sizes. The second patterns are generated from the first patterns and the second dispersion degree is less than the first dispersion degree. The template is separate from the cured coating layer. A size dispersion degree of the patterns used in a nanoimprint lithography process may be adjusted by the light attenuation member, so that the fine patterns may be formed to have an improved size dispersion degree.

    Abstract translation: 在形成精细图案的方法中，在基板上形成光固化涂层。 模板的第一表面与光固化涂层接触。 模板的第一表面包括具有第一分散度大小的至少两个第一图案，并且模板的第一表面的至少一部分包括光衰减构件。 通过模板将光照射到可光固化涂层上，以形成具有第二分散度尺寸的第二图案的固化涂层。 从第一图案生成第二图案，第二色散度小于第一色散度。 模板与固化涂层分开。 可以通过光衰减部件调整在纳米压印光刻工艺中使用的图案的尺寸分散度，使得精细图案可以形成为具有改进的尺寸分散度。

    Semiconductor memory devices including offset active regions
    7.
    发明授权
    Semiconductor memory devices including offset active regions 有权
    包括偏移活动区域的半导体存储器件

    公开(公告)号：US07547936B2

    公开(公告)日：2009-06-16

    申请号：US11246594

    申请日：2005-10-06

    Applicant: Doo-Hoon Goo ,  Han-Ku Cho ,  Joo-Tae Moon ,  Sang-Gyun Woo ,  Gi-Sung Yeo ,  Kyoung-Yun Baek

    Inventor： Doo-Hoon Goo ,  Han-Ku Cho ,  Joo-Tae Moon ,  Sang-Gyun Woo ,  Gi-Sung Yeo ,  Kyoung-Yun Baek

    IPC: H01L271/108

    CPC classification number: H01L27/11502 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10855

    Abstract: A semiconductor memory device may include a substrate having a plurality of active regions and a field isolation layer on the substrate surrounding the active regions of the substrate. Each of the plurality of active regions may have a length in a direction of a first axis and a width in a direction of a second axis, and the length may be greater than the width. The plurality of active regions may be provided in a plurality of columns of active regions in the direction of the second axis, and active regions of adjacent columns may be offset in the direction of the second axis.

    Abstract translation: 半导体存储器件可以包括具有多个有源区的衬底和围绕衬底的有源区的衬底上的场隔离层。 多个有源区域中的每一个可以具有在第一轴线的方向上的长度和在第二轴线的方向上的宽度，并且该长度可以大于宽度。 多个有源区域可以沿着第二轴线的方向设置在多个活性区域列中，并且相邻列的有效区域可以在第二轴线的方向上偏移。

    Method of forming self-aligned contact pads of non-straight type semiconductor memory device
    9.
    发明授权
    Method of forming self-aligned contact pads of non-straight type semiconductor memory device 有权
    形成非直型半导体存储器件的自对准接触焊盘的方法

    公开(公告)号：US07064051B2

    公开(公告)日：2006-06-20

    申请号：US10944151

    申请日：2004-09-16

    Applicant: Eun-Mi Lee ,  Doo-Hoon Goo ,  Jung-Hyeon Lee ,  Gi-Sung Yeo

    Inventor： Eun-Mi Lee ,  Doo-Hoon Goo ,  Jung-Hyeon Lee ,  Gi-Sung Yeo

    IPC: H01L21/3205 ,  H01L21/4763

    CPC classification number: H01L21/76897 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Embodiments of the invention provide methods of forming SAC pads in non-straight semiconductor device having non-straight type or separate type active regions. A plurality of gate line structures extending in one direction may be formed on a semiconductor substrate having non-straight active regions. An interlayer insulating layer covering gate line structures may be formed on the gate line structures. Then, a photo-resist layer may be formed on the interlayer insulating layer. A photo-resist pattern may be formed through exposing and developing the photo-resist layer by using a photo-mask having, for example, a bar type, a wave type, or a reverse active type pattern. Then, contact holes exposing source/drain regions may be formed by etching the interlayer insulating layer using the photo-resist pattern as an etching mask. Contact pads may then be formed by filling the contact holes with a conductive material.

    Abstract translation: 本发明的实施例提供了在具有非直型或分离型有源区的非直线半导体器件中形成SAC焊盘的方法。 可以在具有非直线活性区域的半导体衬底上形成沿一个方向延伸的多个栅极线结构。 覆盖栅极线结构的层间绝缘层可以形成在栅极线结构上。 然后，可以在层间绝缘层上形成光致抗蚀剂层。 可以通过使用具有例如条形，波型或反向活性型图案的光掩模，通过曝光和显影光致抗蚀剂层来形成光刻胶图案。 然后，可以通过使用光刻胶图案作为蚀刻掩模蚀刻层间绝缘层来形成暴露源极/漏极区的接触孔。 然后可以通过用导电材料填充接触孔来形成接触垫。

    Semiconductor memory devices including offset bit lines
    10.
    发明授权
    Semiconductor memory devices including offset bit lines 有权
    包括偏移位线的半导体存储器件

    公开(公告)号：US08013374B2

    公开(公告)日：2011-09-06

    申请号：US12465202

    申请日：2009-05-13

    Applicant: Doo-Hoon Goo ,  Han-Ku Cho ,  Joo-Tae Moon ,  Sang-Gyun Woo ,  Gi-Sung Yeo ,  Kyoung-Yun Baek

    Inventor： Doo-Hoon Goo ,  Han-Ku Cho ,  Joo-Tae Moon ,  Sang-Gyun Woo ,  Gi-Sung Yeo ,  Kyoung-Yun Baek

    IPC: H01L27/108

    CPC classification number: H01L27/10814 ,  H01L27/0207 ,  H01L27/10882 ,  H01L27/11502

    Abstract: A semiconductor memory device may include a substrate having a plurality of active regions wherein each active region has a length in a direction of a first axis and a width in a direction of a second axis. The length may be greater than the width, and the plurality of active regions may be provided in a plurality of columns of active regions in the direction of the second axis. A plurality of wordline pairs may be provided on the substrate, with each wordline pair crossing active regions of a respective column of active regions defining a drain portion of each active region between wordlines of the respective wordline pair. A plurality of bitlines on the substrate may cross the plurality of wordline pairs, with each bitline being electrically coupled to a respective drain portion of an active region of each column, and with each bitline being arranged between the respective drain portion and another drain portion of an adjacent active region of the same column.

    Abstract translation: 半导体存储器件可以包括具有多个有源区的衬底，其中每个有源区具有在第一轴的方向上的长度和在第二轴的方向上的宽度。 长度可以大于宽度，并且多个有源区可以在第二轴的方向上设置在多个有效区列中。 可以在衬底上提供多个字线对，其中每个字线对跨越相应的有效区域列的有源区域，在相应字线对的字线之间限定每个有效区域的漏极部分。 衬底上的多个位线可以跨过多个字线对，每个位线电耦合到每个列的有源区的相应漏极部分，并且每个位线布置在相应的漏极部分和另一个漏极部分的另一个漏极部分之间 相同列的相邻有效区域。

Patent Agency Ranking