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    METAL-INSULATOR-METAL CAPACITOR AND METHOD OF FABRICATION
    3.
    发明申请
    METAL-INSULATOR-METAL CAPACITOR AND METHOD OF FABRICATION 有权
    金属绝缘体 - 金属电容器和制造方法

    公开(公告)号：US20050067701A1

    公开(公告)日：2005-03-31

    申请号：US10605444

    申请日：2003-09-30

    申请人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Jeffrey Gambino ,  Zhong-Xiang He ,  Vidhya Ramachandran

    发明人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Jeffrey Gambino ,  Zhong-Xiang He ,  Vidhya Ramachandran

    IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L23/52 ,  H01L21/44

    CPC分类号： H01L21/7687 ,  H01L23/5223 ,  H01L23/53238 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method and structure for a MIM capacitor, the structure including: an electronic device, comprising: an interlevel dielectric layer formed on a semiconductor substrate; a copper bottom electrode formed in the interlevel dielectric layer, a top surface of the bottom electrode co-planer with a top surface of the interlevel dielectric layer; a conductive diffusion barrier in direct contact with the top surface of the bottom electrode; a MIM dielectric in direct contact with a top surface of the conductive diffusion barrier; and a top electrode in direct contact with a top surface of the MIM dielectric. The conductive diffusion barrier may be recessed into the copper bottom electrode or an additional recessed conductive diffusion barrier provided. Compatible resistor and alignment mark structures are also disclosed.

    摘要翻译： 一种MIM电容器的方法和结构，该结构包括：电子器件，包括：形成在半导体衬底上的层间电介质层; 形成在所述层间电介质层中的铜底电极，所述底电极共平面的上表面与所述层间电介质层的顶面形成; 与底部电极的顶表面直接接触的导电扩散阻挡层; 与所述导电扩散阻挡层的顶表面直接接触的MIM电介质; 以及与MIM电介质的顶表面直接接触的顶部电极。 导电扩散阻挡层可以凹进到铜底电极或设置的另外的凹入的导电扩散阻挡层中。 还公开了兼容的电阻器和对准标记结构。

    INEXPENSIVE METHOD OF FABRICATING A HIGHER PERFORMANCE CAPACITANCE DENSITY MIMCAP INTEGRABLE INTO A COPPER INTERCONNECT SCHEME
    4.
    发明申请
    INEXPENSIVE METHOD OF FABRICATING A HIGHER PERFORMANCE CAPACITANCE DENSITY MIMCAP INTEGRABLE INTO A COPPER INTERCONNECT SCHEME 失效
    将高性能电容密度MIMCAP合并成一个铜互连方案的独立方法

    公开(公告)号：US20070290359A1

    公开(公告)日：2007-12-20

    申请号：US11846248

    申请日：2007-08-28

    申请人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Zhong-Xiang He ,  William Murphy ,  Vidhya Ramachandran

    发明人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Zhong-Xiang He ,  William Murphy ,  Vidhya Ramachandran

    IPC分类号： H01L23/48

    CPC分类号： H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method to integrate MIM capacitors into conductive interconnect levels, with low cost impact, and high yield, reliability and performance than existing integration methods is provided. This is accomplished by recessing a prior level dielectric for MIM capacitor level alignment followed by deposition and patterning of the MIM capacitor films. Specifically, the method includes providing a substrate including a wiring level, the wiring level comprising at least one conductive interconnect formed in a dielectric layer; selectively removing a portion of the dielectric layer to recess the dielectric layer below an upper surface of the at least one conductive interconnect; forming a dielectric stack upon the at least one conductive interconnect and the recessed dielectric layer; and forming a metal-insulator-metal (MIM) capacitor on the dielectric stack. The MIM capacitor includes a bottom plate electrode, a dielectric and a top plate electrode. The bottom and top plate electrodes can comprise the same or different conductive metal.

    摘要翻译： 提供了一种将MIM电容器集成到导电互连级别中的方法，具有低成本影响，并且提供了比现有集成方法高的产量，可靠性和性能。 这通过将用于MIM电容器电平对准的先前级别的电介质凹入，然后MIM电容器膜的沉积和图案化来实现。 具体地，该方法包括提供包括布线层的衬底，所述布线层包括形成在电介质层中的至少一个导电布线; 选择性地去除所述电介质层的一部分以使所述电介质层在所述至少一个导电互连的上表面下方凹陷; 在所述至少一个导电互连和所述凹入的介电层上形成电介质叠层; 以及在介电叠层上形成金属绝缘体金属（MIM）电容器。 MIM电容器包括底板电极，电介质和顶板电极。 底板和顶板电极可以包括相同或不同的导电金属。

    Metal-insulator-metal capacitor and method of fabrication
    5.
    发明申请
    Metal-insulator-metal capacitor and method of fabrication 审中-公开
    金属绝缘体金属电容器及其制造方法

    公开(公告)号：US20050156278A1

    公开(公告)日：2005-07-21

    申请号：US11028425

    申请日：2005-01-03

    申请人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Jeffrey Gambino ,  Zhong-Xiang He ,  Vidhya Ramachandran

    发明人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Jeffrey Gambino ,  Zhong-Xiang He ,  Vidhya Ramachandran

    IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/48 ,  H01L29/00

    CPC分类号： H01L21/7687 ,  H01L23/5223 ,  H01L23/53238 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method and structure for a MIM capacitor, the structure including: an electronic device, comprising: an interlevel dielectric layer formed on a semiconductor substrate; a copper bottom electrode formed in the interlevel dielectric layer, a top surface of the bottom electrode co-planer with a top surface of the interlevel dielectric layer; a conductive diffusion barrier in direct contact with the top surface of the bottom electrode; a MIM dielectric in direct contact with a top surface of the conductive diffusion barrier; and a top electrode in direct contact with a top surface of the MIM dielectric. The conductive diffusion barrier may be recessed into the copper bottom electrode or an additional recessed conductive diffusion barrier provided. Compatible resistor and alignment mark structures are also disclosed.

    摘要翻译： 一种MIM电容器的方法和结构，该结构包括：电子器件，包括：形成在半导体衬底上的层间电介质层; 形成在所述层间电介质层中的铜底电极，所述底电极共平面的顶面与所述层间电介质层的顶面形成; 与底部电极的顶表面直接接触的导电扩散阻挡层; 与所述导电扩散阻挡层的顶表面直接接触的MIM电介质; 以及与MIM电介质的顶表面直接接触的顶部电极。 导电扩散阻挡层可以凹进到铜底电极或设置的另外的凹入的导电扩散阻挡层中。 还公开了兼容的电阻器和对准标记结构。

    INEXPENSIVE METHOD OF FABRICATING A HIGHER PERFORMANCE CAPACITANCE DENSITY MIMCAP INTEGRABLE INTO A COPPER INTERCONNECT SCHEME
    7.
    发明申请
    INEXPENSIVE METHOD OF FABRICATING A HIGHER PERFORMANCE CAPACITANCE DENSITY MIMCAP INTEGRABLE INTO A COPPER INTERCONNECT SCHEME 有权
    将高性能电容密度MIMCAP合并成一个铜互连方案的独立方法

    公开(公告)号：US20050274987A1

    公开(公告)日：2005-12-15

    申请号：US10709829

    申请日：2004-06-01

    申请人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Zhong-Xiang He ,  William Murphy ,  Vidhya Ramachandran

    发明人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Zhong-Xiang He ,  William Murphy ,  Vidhya Ramachandran

    IPC分类号： H01L21/00 ,  H01L23/52 ,  H01L23/522

    CPC分类号： H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method to integrate MIM capacitors into conductive interconnect levels, with low cost impact, and high yield, reliability and performance than existing integration methods is provided. This is accomplished by recessing a prior level dielectric for MIM capacitor level alignment followed by deposition and patterning of the MIM capacitor films. Specifically, the method includes providing a substrate including a wiring level, the wiring level comprising at least one conductive interconnect formed in a dielectric layer; selectively removing a portion of the dielectric layer to recess the dielectric layer below an upper surface of the at least one conductive interconnect; forming a dielectric stack upon the at least one conductive interconnect and the recessed dielectric layer; and forming a metal-insulator-metal (MIM) capacitor on the dielectric stack. The MIM capacitor includes a bottom plate electrode, a dielectric and a top plate electrode. The bottom and top plate electrodes can comprise the same or different conductive metal.

    摘要翻译： 提供了一种将MIM电容器集成到导电互连级别中的方法，具有低成本影响，并且提供了比现有集成方法高的产量，可靠性和性能。 这通过将用于MIM电容器电平对准的先前级别的电介质凹入，然后MIM电容器膜的沉积和图案化来实现。 具体地，该方法包括提供包括布线层的衬底，所述布线层包括形成在电介质层中的至少一个导电布线; 选择性地去除所述电介质层的一部分以使所述电介质层在所述至少一个导电互连的上表面下方凹陷; 在所述至少一个导电互连和所述凹入的介电层上形成电介质叠层; 以及在介电叠层上形成金属绝缘体金属（MIM）电容器。 MIM电容器包括底板电极，电介质和顶板电极。 底板和顶板电极可以包括相同或不同的导电金属。

    INTEGRATED THIN-FILM RESISTOR WITH DIRECT CONTACT
    8.
    发明申请
    INTEGRATED THIN-FILM RESISTOR WITH DIRECT CONTACT 失效
    集成薄膜电阻与直接接触

    公开(公告)号：US20070166909A1

    公开(公告)日：2007-07-19

    申请号：US11275611

    申请日：2006-01-19

    申请人： Eric Coker ,  Douglas Coolbaugh ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Matthew Moon ,  Anthony Stamper

    发明人： Eric Coker ,  Douglas Coolbaugh ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Matthew Moon ,  Anthony Stamper

    IPC分类号： H01L21/8244

    CPC分类号： H01L27/016

    摘要： A BEOL thin-film resistor adapted for flexible integration rests on a first layer of ILD. The thickness of the first layer of ILD and the resistor thickness combine to match the nominal design thickness of vias in the layer of concern. A second layer of ILD matches the resistor thickness and is planarized to the top surface of the resistor. A third layer of ILD has a thickness equal to the nominal value of the interconnections on this layer. *Dual damascene interconnection apertures and apertures for making contact with the resistor are formed simultaneously, with the etch stop upper cap layer in the resistor protecting the resistive layer while the vias in the dual damascene apertures are formed.

    摘要翻译： 适用于灵活集成的BEOL薄膜电阻依赖于第一层ILD。 ILD的第一层的厚度和电阻器厚度相结合，以匹配所涉及的层中的通孔的标称设计厚度。 第二层ILD匹配电阻器厚度，并平坦化到电阻器的顶表面。 ILD的第三层具有等于该层上互连的标称值的厚度。 同时形成用于与电阻器接触的双镶嵌互连孔和孔，电阻器中的蚀刻停止上盖层保护电阻层，同时形成双镶嵌孔中的通孔。

    INTEGRATED THIN-FILM RESISTOR WITH DIRECT CONTACT
    9.
    发明申请
    INTEGRATED THIN-FILM RESISTOR WITH DIRECT CONTACT 有权
    集成薄膜电阻与直接接触

    公开(公告)号：US20070290272A1

    公开(公告)日：2007-12-20

    申请号：US11846595

    申请日：2007-08-29

    申请人： Eric Coker ,  Douglas Coolbaugh ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Matthew Moon ,  Anthony Stamper

    发明人： Eric Coker ,  Douglas Coolbaugh ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Matthew Moon ,  Anthony Stamper

    IPC分类号： H01L29/00

    CPC分类号： H01L27/016

    摘要： A BEOL thin-film resistor adapted for flexible integration rests on a first layer of ILD. The thickness of the first layer of ILD and the resistor thickness combine to match the nominal design thickness of vias in the layer of concern. A second layer of ILD matches the resistor thickness and is planarized to the top surface of the resistor. A third layer of ILD has a thickness equal to the nominal value of the interconnections on this layer. Dual damascene interconnection apertures and apertures for making contact with the resistor are formed simultaneously, with the etch stop upper cap layer in the resistor protecting the resistive layer while the vias in the dual damascene apertures are formed.

    摘要翻译： 适用于灵活集成的BEOL薄膜电阻依赖于第一层ILD。 ILD的第一层的厚度和电阻器厚度相结合，以匹配所涉及的层中的通孔的标称设计厚度。 第二层ILD匹配电阻器厚度，并平坦化到电阻器的顶表面。 ILD的第三层具有等于该层上互连的标称值的厚度。 同时形成用于与电阻器接触的双镶嵌互连孔和孔，电阻器中的蚀刻停止上盖层保护电阻层，同时形成双镶嵌孔中的通孔。