公开(公告)号：US20070166909A1

公开(公告)日：2007-07-19

申请号：US11275611

申请日：2006-01-19

申请人： Eric Coker ,  Douglas Coolbaugh ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Matthew Moon ,  Anthony Stamper

发明人： Eric Coker ,  Douglas Coolbaugh ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Matthew Moon ,  Anthony Stamper

IPC分类号： H01L21/8244

CPC分类号： H01L27/016

摘要： A BEOL thin-film resistor adapted for flexible integration rests on a first layer of ILD. The thickness of the first layer of ILD and the resistor thickness combine to match the nominal design thickness of vias in the layer of concern. A second layer of ILD matches the resistor thickness and is planarized to the top surface of the resistor. A third layer of ILD has a thickness equal to the nominal value of the interconnections on this layer. *Dual damascene interconnection apertures and apertures for making contact with the resistor are formed simultaneously, with the etch stop upper cap layer in the resistor protecting the resistive layer while the vias in the dual damascene apertures are formed.

摘要翻译： 适用于灵活集成的BEOL薄膜电阻依赖于第一层ILD。 ILD的第一层的厚度和电阻器厚度相结合，以匹配所涉及的层中的通孔的标称设计厚度。 第二层ILD匹配电阻器厚度，并平坦化到电阻器的顶表面。 ILD的第三层具有等于该层上互连的标称值的厚度。 同时形成用于与电阻器接触的双镶嵌互连孔和孔，电阻器中的蚀刻停止上盖层保护电阻层，同时形成双镶嵌孔中的通孔。

公开(公告)号：US20070290272A1

公开(公告)日：2007-12-20

申请号：US11846595

申请日：2007-08-29

申请人： Eric Coker ,  Douglas Coolbaugh ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Matthew Moon ,  Anthony Stamper

发明人： Eric Coker ,  Douglas Coolbaugh ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Matthew Moon ,  Anthony Stamper

IPC分类号： H01L29/00

CPC分类号： H01L27/016

摘要： A BEOL thin-film resistor adapted for flexible integration rests on a first layer of ILD. The thickness of the first layer of ILD and the resistor thickness combine to match the nominal design thickness of vias in the layer of concern. A second layer of ILD matches the resistor thickness and is planarized to the top surface of the resistor. A third layer of ILD has a thickness equal to the nominal value of the interconnections on this layer. Dual damascene interconnection apertures and apertures for making contact with the resistor are formed simultaneously, with the etch stop upper cap layer in the resistor protecting the resistive layer while the vias in the dual damascene apertures are formed.

摘要翻译： 适用于灵活集成的BEOL薄膜电阻依赖于第一层ILD。 ILD的第一层的厚度和电阻器厚度相结合，以匹配所涉及的层中的通孔的标称设计厚度。 第二层ILD匹配电阻器厚度，并平坦化到电阻器的顶表面。 ILD的第三层具有等于该层上互连的标称值的厚度。 同时形成用于与电阻器接触的双镶嵌互连孔和孔，电阻器中的蚀刻停止上盖层保护电阻层，同时形成双镶嵌孔中的通孔。

公开(公告)号：US20070158714A1

公开(公告)日：2007-07-12

申请号：US11164382

申请日：2005-11-21

申请人： Ebenezer Eshun ,  Jessie Abbotts ,  Daniel Colello ,  Douglas Coolbaugh ,  Zhong-Xiang He ,  Matthew Moon ,  Charles Musante ,  Robert Rassel

发明人： Ebenezer Eshun ,  Jessie Abbotts ,  Daniel Colello ,  Douglas Coolbaugh ,  Zhong-Xiang He ,  Matthew Moon ,  Charles Musante ,  Robert Rassel

IPC分类号： H01L29/94

CPC分类号： H01L28/60 ,  H01L21/76895

摘要： A MIM capacitor technique is described wherein bottom plates (electrodes) are composed of gate conductor material, and are formed in the same layer, in the same way, using the same masking and processing steps as transistor gates. The top plates (electrodes) are formed using a simple single-mask, single-damascene process. Electrical connections to both electrodes of the MIM capacitor are made via conventional BEOL metallization, requiring no additional dedicated process steps. The bottom plates (formed of gate conductor material) of the MIM capacitors overlie STI regions formed at the same time as STI regions between transistors. Method and apparatus are described.

摘要翻译： 描述了MIM电容器技术，其中底板（电极）由栅极导体材料构成，并且以相同的方式使用与晶体管栅极相同的掩模和处理步骤形成在相同的层中。 顶板（电极）使用简单的单掩模，单镶嵌工艺形成。 与MIM电容器的两个电极的电连接通过常规BEOL金属化制成，不需要额外的专用工艺步骤。 MIM电容器的底板（由栅极导体材料形成）覆盖与晶体管之间的STI区域同时形成的STI区域。 描述了方法和装置。

公开(公告)号：US20080019077A1

公开(公告)日：2008-01-24

申请号：US11838939

申请日：2007-08-15

申请人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Natalie Feilchenfeld ,  Michael Gautsch ,  Zhong-Xiang He ,  Matthew Moon ,  Vidhya Rahmachandran ,  Barbara Waterhouse

发明人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Natalie Feilchenfeld ,  Michael Gautsch ,  Zhong-Xiang He ,  Matthew Moon ,  Vidhya Rahmachandran ,  Barbara Waterhouse

IPC分类号： H01G4/06 ,  H01S4/00

CPC分类号： H01L23/5223 ,  H01L27/016 ,  H01L27/0805 ,  H01L28/40 ,  H01L2924/0002 ,  Y10T29/49002 ,  H01L2924/00

摘要： Disclosed is a method of fabricating a metal-insulator-metal (MIM) capacitor. In this method, a dielectric layer is formed above a lower conductor layer and an upper conductor layer is formed above the dielectric layer. The invention then forms an etch stop layer above the upper conductor layer and the dielectric layer, and forms a hardmask (silicon oxide hardmask, a silicon nitride hardmask, etc.) over the etch stop layer. Next, a photoresist is patterned above the hardmask, which allows the hardmask, the etch stop layer, the dielectric layer, and the lower conductor layer to be etched through the photoresist.

摘要翻译： 公开了一种制造金属 - 绝缘体 - 金属（MIM）电容器的方法。 在该方法中，在下导体层的上方形成电介质层，在电介质层的上方形成上导体层。 然后，本发明在上导体层和电介质层之上形成蚀刻停止层，并在蚀刻停止层上形成硬掩模（氧化硅硬掩模，氮化硅硬掩模等）。 接下来，在硬掩模上形成光致抗蚀剂，这允许通过光致抗蚀剂蚀刻硬掩模，蚀刻停止层，电介质层和下导体层。

公开(公告)号：US20050272219A1

公开(公告)日：2005-12-08

申请号：US10709907

申请日：2004-06-04

申请人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Natalie Feilchenfeld ,  Michael Gautsch ,  Zhong-Xiang He ,  Matthew Moon ,  Vidhya Ramachandran ,  Barbara Waterhouse

发明人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Natalie Feilchenfeld ,  Michael Gautsch ,  Zhong-Xiang He ,  Matthew Moon ,  Vidhya Ramachandran ,  Barbara Waterhouse

IPC分类号： H01L21/02 ,  H01L21/20 ,  H01L21/8242 ,  H01L27/01 ,  H01L27/08

CPC分类号： H01L23/5223 ,  H01L27/016 ,  H01L27/0805 ,  H01L28/40 ,  H01L2924/0002 ,  Y10T29/49002 ,  H01L2924/00

摘要： Disclosed is a method of fabricating a metal-insulator-metal (MIM) capacitor. In this method, a dielectric layer is formed above a lower conductor layer and an upper conductor layer is formed above the dielectric layer. The invention then forms an etch stop layer above the upper conductor layer and the dielectric layer, and forms a hardmask (silicon oxide hardmask, a silicon nitride hardmask, etc.) over the etch stop layer. Next, a photoresist is patterned above the hardmask, which allows the hardmask, the etch stop layer, the dielectric layer, and the lower conductor layer to be etched through the photoresist.

摘要翻译： 公开了一种制造金属 - 绝缘体 - 金属（MIM）电容器的方法。 在该方法中，在下导体层的上方形成电介质层，在电介质层的上方形成上导体层。 然后，本发明在上导体层和电介质层之上形成蚀刻停止层，并在蚀刻停止层上形成硬掩模（氧化硅硬掩模，氮化硅硬掩模等）。 接下来，在硬掩模上形成光致抗蚀剂，这允许通过光致抗蚀剂蚀刻硬掩模，蚀刻停止层，电介质层和下导体层。

公开(公告)号：US20070187787A1

公开(公告)日：2007-08-16

申请号：US11276160

申请日：2006-02-16

申请人： Kristin Ackerson ,  James Adkisson ,  John Ellis-Monaghan ,  Jeffrey Gambino ,  Timothy Hoague ,  Mark Jaffe ,  Robert Leidy ,  Matthew Moon ,  Richard Passel

发明人： Kristin Ackerson ,  James Adkisson ,  John Ellis-Monaghan ,  Jeffrey Gambino ,  Timothy Hoague ,  Mark Jaffe ,  Robert Leidy ,  Matthew Moon ,  Richard Passel

IPC分类号： H01L27/14

CPC分类号： H01L27/14643 ,  H01L27/14625 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14685 ,  H01L27/14687 ,  H01L27/14689

摘要： A pixel for an image sensor includes a photosensor located within a substrate. A patterned dielectric layer having an aperture registered with the photosensor is located over the substrate. A lens structure is located over the dielectric layer and also registered with the photosensor. A liner layer is located contiguously upon a top surface of the dielectric layer, and the sidewalls and bottom of the aperture. The liner layer provides for enhanced reflection for off-axis incoming light and enhanced capture thereof by the photosensor. When the aperture does not provide a dielectric layer border for a metallization layer embedded within the dielectric layer, an exposed edge of the metallization layer may be chamfered.

摘要翻译： 用于图像传感器的像素包括位于衬底内的光电传感器。 具有与光电传感器对准的孔径的图案化电介质层位于衬底上。 透镜结构位于电介质层上方并且还与光电传感器配准。 衬垫层连续地定位在电介质层的顶表面上，孔的侧壁和底部。 衬垫层为离轴入射光提供增强的反射，并且通过光电传感器增强其捕获。 当孔径不为嵌入在电介质层内的金属化层提供介电层边界时，金属化层的暴露边缘可以被倒角。