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公开(公告)号：US07714412B2
公开(公告)日：2010-05-11
申请号：US10711144
申请日：2004-08-27
IPC分类号： H01L29/93
摘要： The present invention provides a varactor that has increased tunability and a high quality factor Q as well as a method of fabricating the varactor. The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes providing a structure that includes a semiconductor substrate of a first conductivity type and optionally a subcollector or isolation well (i.e., doped region) of a second conductivity type located below an upper region of the substrate, the first conductivity type is different from said second conductivity type. Next, a plurality of isolation regions are formed in the upper region of the substrate and then a well region is formed in the upper region of the substrate. In some cases, the doped region is formed at this point of the inventive process. The well region includes outer well regions of the second conductivity type and an inner well region of the first conductivity type. Each well of said well region is separated at an upper surface by an isolation region. A field effect transistor having at least a gate conductor of the first conductivity type is then formed above the inner well region.
摘要翻译： 本发明提供一种具有增加的可调性和高品质因数Q的变容二极管以及制造变容二极管的方法。 本发明的方法可以集成到常规的CMOS处理方案中，或者被整合到常规的BiCMOS处理方案中。 该方法包括提供包括第一导电类型的半导体衬底和位于衬底的上部区域下方的第二导电类型的子集电极或隔离阱（即，掺杂区）的结构，第一导电类型不同于 所述第二导电类型。 接下来，在基板的上部区域形成多个隔离区域，然后在基板的上部区域形成阱区域。 在一些情况下，在本发明方法的这一点形成掺杂区域。 阱区包括第二导电类型的外阱区和第一导电类型的内阱区。 所述阱区的每个阱在上表面被隔离区分开。 然后形成至少具有第一导电类型的栅极导体的场效应晶体管，并在内部阱区域的上方形成。
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2.发明申请ASYMMETRIC SILICON-ON-INSULATOR (SOI) JUNCTION FIELD EFFECT TRANSISTOR (JFET), A METHOD OF FORMING THE ASYMMETRICAL SOI JFET, AND A DESIGN STRUCTURE FOR THE ASYMMETRICAL SOI JFET 有权不对称硅绝缘体（SOI）结场效应晶体管（JFET），形成非对称SOI JFET的方法和非对称SOI JFET的设计结构公开(公告)号：US20110284930A1
公开(公告)日：2011-11-24
申请号：US12784583
申请日：2010-05-21
申请人： Douglas B. Hershberger , Richard A. Phelps , Robert M. Rassel , Stephen A. St. Onge , Michael J. Zierak
发明人： Douglas B. Hershberger , Richard A. Phelps , Robert M. Rassel , Stephen A. St. Onge , Michael J. Zierak
IPC分类号： H01L29/812 , H01L21/782 , G06F17/50 , H01L27/12
CPC分类号： G06F17/5068 , H01L21/84 , H01L27/1203 , H01L29/0649 , H01L29/0843 , H01L29/66901 , H01L29/8086
摘要： An asymmetric silicon-on-insulator (SOI) junction field effect transistor (JFET) and a method. The JFET includes a bottom gate on an insulator layer, a channel region on the bottom gate and, on the channel region, source/drain regions and a top gate between the source/drain regions. STIs isolate the source/drain regions from the top gate and a DTI laterally surrounds the JFET to isolate it from other devices. Non-annular well(s) are positioned adjacent to the channel region and bottom gate (e.g., a well having the same conductivity type as the top and bottom gates can be connected to the top gate and can extend down to the insulator layer, forming a gate contact on only a portion of the channel region, and/or another well having the same conductivity type as the channel and source/drain regions can extend from the source region to the insulator layer, forming a source-to-channel strap).
摘要翻译： 不对称绝缘体上硅（SOI）结场效应晶体管（JFET）及其方法。 JFET包括在绝缘体层上的底栅极，底栅上的沟道区，以及沟道区上的源/漏区和源/漏区之间的顶栅。 STI将源极/漏极区域与顶部栅极隔离，并且DTI横向围绕JFET以将其与其它器件隔离。 非环形阱位于与沟道区域和底部栅极相邻的位置（例如，具有与顶部和底部栅极相同的导电类型的阱可以连接到顶部栅极并且可以向下延伸到绝缘体层，形成 在沟道区域的仅一部分上的栅极接触和/或具有与沟道和源极/漏极区相同的导电类型的另一个阱可以从源极区域延伸到绝缘体层，形成源极至沟道的带） 。
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3.发明授权Asymmetric silicon-on-insulator (SOI) junction field effect transistor (JFET) and a method of forming the asymmetrical SOI JFET 有权非对称绝缘体上硅（SOI）结场效应晶体管（JFET）和形成非对称SOI JFET的方法公开(公告)号：US08466501B2
公开(公告)日：2013-06-18
申请号：US12784583
申请日：2010-05-21
申请人： Douglas B. Hershberger , Richard A. Phelps , Robert M. Rassel , Stephen A. St. Onge , Michael J. Zierak
发明人： Douglas B. Hershberger , Richard A. Phelps , Robert M. Rassel , Stephen A. St. Onge , Michael J. Zierak
IPC分类号： H01L29/808
CPC分类号： G06F17/5068 , H01L21/84 , H01L27/1203 , H01L29/0649 , H01L29/0843 , H01L29/66901 , H01L29/8086
摘要： An asymmetric silicon-on-insulator (SOI) junction field effect transistor (JFET) and a method. The JFET includes a bottom gate on an insulator layer, a channel region on the bottom gate and, on the channel region, source/drain regions and a top gate between the source/drain regions. STIs isolate the source/drain regions from the top gate and a DTI laterally surrounds the JFET to isolate it from other devices. Non-annular well(s) are positioned adjacent to the channel region and bottom gate (e.g., a well having the same conductivity type as the top and bottom gates can be connected to the top gate and can extend down to the insulator layer, forming a gate contact on only a portion of the channel region, and/or another well having the same conductivity type as the channel and source/drain regions can extend from the source region to the insulator layer, forming a source-to-channel strap).
摘要翻译： 不对称绝缘体上硅（SOI）结场效应晶体管（JFET）及其方法。 JFET包括在绝缘体层上的底栅极，底栅上的沟道区，以及沟道区上的源/漏区和源/漏区之间的顶栅。 STI将源极/漏极区域与顶部栅极隔离，并且DTI横向围绕JFET以将其与其它器件隔离。 非环形阱位于与沟道区域和底部栅极相邻的位置（例如，具有与顶部和底部栅极相同的导电类型的阱可以连接到顶部栅极并且可以向下延伸到绝缘体层，形成 在沟道区域的仅一部分上的栅极接触和/或具有与沟道和源极/漏极区相同的导电类型的另一个阱可以从源极区域延伸到绝缘体层，形成源极至沟道的带） 。
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公开(公告)号：US20130140668A1
公开(公告)日：2013-06-06
申请号：US13312442
申请日：2011-12-06
申请人： Alan B. Botula , Renata Camillo-Castillo , James S. Dunn , Jeffrey P. Gambino , Douglas B. Hershberger , Alvin J. Joseph , Mark E. Stidham , Robert M. Rassel
发明人： Alan B. Botula , Renata Camillo-Castillo , James S. Dunn , Jeffrey P. Gambino , Douglas B. Hershberger , Alvin J. Joseph , Mark E. Stidham , Robert M. Rassel
CPC分类号： H01L21/76224 , H01L21/26506 , H01L21/823892 , H01L27/04 , H01L27/0623 , H01L27/0635 , H01L27/0802 , H01L27/0811 , H01L27/0928
摘要： A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices.
摘要翻译： 衬底包括具有第一电阻率的第一区域，用于优化场效应晶体管，具有第二电阻率的第二区域，用于优化双极晶体管器件和三阱的npn子集电极，具有第三电阻率的第三区域，具有第三电阻率 用于无源器件的高电阻率，第四区域，基本上没有植入，以为器件提供低周边电容。
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公开(公告)号：US07393701B2
公开(公告)日：2008-07-01
申请号：US11566887
申请日：2006-12-05
IPC分类号： H01L21/302 , H01L21/308
摘要： Methods of adjusting a resistance of a buried resistor in a semiconductor are disclosed. In one aspect, the method includes using a silicidation blocking mask to define the buried resistor in the semiconductor; adjusting a size of the silicidation blocking mask to adjust a resistance of the buried resistor based on test data from a previous processing lot including a substantially similar buried resistor; and forming silicide on an area not covered by the silicidation blocking mask. The adjustment may be made by balancing the amount of the resistor that is covered with silicide versus un-silicided semiconductor to achieve the desired total resistance. The adjustment may be made according to an algorithm.
摘要翻译： 公开了调整半导体中的埋入电阻的电阻的方法。 一方面，该方法包括使用硅化阻挡掩模来限定半导体中的掩埋电阻; 调整硅化阻挡掩模的尺寸以根据来自包括基本相似的掩埋电阻器的先前处理批次的测试数据来调整埋入电阻器的电阻; 并且在未被硅化阻挡掩模覆盖的区域上形成硅化物。 可以通过平衡用硅化物覆盖的电阻器与非硅化半导体的量来实现所需的总电阻来进行调整。 可以根据算法进行调整。
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公开(公告)号：US20080131980A1
公开(公告)日：2008-06-05
申请号：US11566887
申请日：2006-12-05
摘要： Methods of adjusting a resistance of a buried resistor in a semiconductor are disclosed. In one aspect, the method includes using a silicidation blocking mask to define the buried resistor in the semiconductor; adjusting a size of the silicidation blocking mask to adjust a resistance of the buried resistor based on test data from a previous processing lot including a substantially similar buried resistor; and forming silicide on an area not covered by the silicidation blocking mask. The adjustment may be made by balancing the amount of the resistor that is covered with silicide versus un-silicided semiconductor to achieve the desired total resistance. The adjustment may be made according to an algorithm.
摘要翻译： 公开了调整半导体中的埋入电阻的电阻的方法。 一方面，该方法包括使用硅化阻挡掩模来限定半导体中的掩埋电阻; 调整硅化阻挡掩模的尺寸以根据来自包括基本相似的掩埋电阻器的先前处理批次的测试数据来调整埋入电阻器的电阻; 并且在未被硅化阻挡掩模覆盖的区域上形成硅化物。 可以通过平衡用硅化物覆盖的电阻器与非硅化半导体的量来实现所需的总电阻来进行调整。 可以根据算法进行调整。
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公开(公告)号：US08735986B2
公开(公告)日：2014-05-27
申请号：US13312442
申请日：2011-12-06
申请人： Alan B. Botula , Renata Camillo-Castillo , James S. Dunn , Jeffrey P. Gambino , Douglas B. Hershberger , Alvin J. Joseph , Robert M. Rassel , Mark E. Stidham
发明人： Alan B. Botula , Renata Camillo-Castillo , James S. Dunn , Jeffrey P. Gambino , Douglas B. Hershberger , Alvin J. Joseph , Robert M. Rassel , Mark E. Stidham
IPC分类号： H01L27/12
CPC分类号： H01L21/76224 , H01L21/26506 , H01L21/823892 , H01L27/04 , H01L27/0623 , H01L27/0635 , H01L27/0802 , H01L27/0811 , H01L27/0928
摘要： A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices.
摘要翻译： 衬底包括具有第一电阻率的第一区域，用于优化场效应晶体管，具有第二电阻率的第二区域，用于优化双极晶体管器件和三阱的npn子集电极，具有第三电阻率的第三区域，具有第三电阻率 用于无源器件的高电阻率，第四区域，基本上没有植入，以为器件提供低周边电容。
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公开(公告)号：US07807562B2
公开(公告)日：2010-10-05
申请号：US12256221
申请日：2008-10-22
IPC分类号： H01L21/4763
CPC分类号： H01L21/76838
摘要： A circuit is provided which prevents dendrite formation on interconnects during semiconductor device processing due to a dendrite-forming current. The circuit includes a switch located in at least one of the dendrite-forming current paths. The switch is configured to be open or in the “off” state during processing, and is configured to be closed or in the “on” state after processing to allow proper functioning of the semiconductor device. The switch may include an nFET or pFET, depending on the environment in which it is used to control or prevent dendrite formation. The switch may be configured to change to the “closed” state when an input signal is provided during operation of the fabricated semiconductor device.
摘要翻译： 提供了一种电路，其防止由于树突形成电流而在半导体器件处理期间互连上的枝晶形成。 电路包括位于至少一个枝晶形成电流路径中的开关。 该开关被配置为在处理期间处于打开状态或处于“关闭”状态，并且在处理之后被配置为闭合或处于“接通”状态以允许半导体器件正常工作。 开关可以包括nFET或pFET，这取决于其用于控制或防止枝晶形成的环境。 当在制造的半导体器件的操作期间提供输入信号时，开关可以被配置为改变为“闭合”状态。
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公开(公告)号：US20090035933A1
公开(公告)日：2009-02-05
申请号：US12256221
申请日：2008-10-22
IPC分类号： H01L21/4763
CPC分类号： H01L21/76838
摘要： A circuit is provided which prevents dendrite formation on interconnects during semiconductor device processing due to a dendrite-forming current. The circuit includes a switch located in at least one of the dendrite-forming current paths. The switch is configured to be open or in the “off” state during processing, and is configured to be closed or in the “on” state after processing to allow proper functioning of the semiconductor device. The switch may include an nFET or pFET, depending on the environment in which it is used to control or prevent dendrite formation. The switch may be configured to change to the “closed” state when an input signal is provided during operation of the fabricated semiconductor device.
摘要翻译： 提供一种电路，其防止由于树突形成电流而在半导体器件处理期间互连上的枝晶形成。 电路包括位于至少一个枝晶形成电流路径中的开关。 该开关被配置为在处理期间处于打开状态或处于“关闭”状态，并且在处理之后被配置为闭合或处于“接通”状态以允许半导体器件正常工作。 开关可以包括nFET或pFET，这取决于其用于控制或防止枝晶形成的环境。 当在制造的半导体器件的操作期间提供输入信号时，开关可以被配置为改变为“闭合”状态。
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公开(公告)号：US07473643B2
公开(公告)日：2009-01-06
申请号：US11461623
申请日：2006-08-01
IPC分类号： H01L21/44
CPC分类号： H01L21/76838
摘要： A circuit is provided which prevents dendrite formation on interconnects during semiconductor device processing due to a dendrite-forming current. The circuit includes a switch located in at least one of the dendrite-forming current paths. The switch is configured to be open or in the “off” state during processing, and is configured to be closed or in the “on” state after processing to allow proper functioning of the semiconductor device. The switch may include an nFET or pFET, depending on the environment in which it is used to control or prevent dendrite formation. The switch may be configured to change to the “closed” state when an input signal is provided during operation of the fabricated semiconductor device.
摘要翻译： 提供一种电路，其防止由于树突形成电流而在半导体器件处理期间互连上的枝晶形成。 电路包括位于至少一个枝晶形成电流路径中的开关。 该开关被配置为在处理期间处于打开状态或处于“关闭”状态，并且在处理之后被配置为闭合或处于“接通”状态以允许半导体器件正常工作。 开关可以包括nFET或pFET，这取决于其用于控制或防止枝晶形成的环境。 当在制造的半导体器件的操作期间提供输入信号时，开关可以被配置为改变为“闭合”状态。
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