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公开(公告)号：US06219754B1
公开(公告)日：2001-04-17
申请号：US08994489
申请日：1997-12-19
IPC分类号： G06F1200
CPC分类号： G06F12/0875
摘要： A dedicated bus between a central processing unit and a peripheral unit, such as a graphics controller driving a video display, provides enhanced capability in an environment in which signal processing occurs within the central processing unit. The dedicated bus relieves other data buses, such as the PCI bus, of the need to communicate large amounts of data, such as decompressed video data. The resulting system supports high bandwidth transmissions of decompressed video data, enabling high resolution 24 bit full motion video and multiple data stream video.
摘要翻译： 在中央处理单元和周边单元之间的专用总线，例如驱动视频显示器的图形控制器，在中央处理单元内发生信号处理的环境中提供增强的能力。 专用总线减轻了诸如PCI总线的其他数据总线，需要传送大量数据，例如解压缩的视频数据。 所得到的系统支持解压缩视频数据的高带宽传输，实现高分辨率24位全动态视频和多数据流视频。
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2.发明授权
公开(公告)号：US5625829A
公开(公告)日：1997-04-29
申请号：US276250
申请日：1994-07-18
IPC分类号： G06F15/173 , G06F1/16 , G06F13/36 , G06F13/364 , G06F13/40 , G06F3/00
CPC分类号： G06F13/364 , G06F1/1632 , G06F13/4036 , G06F13/4081
摘要： A dockable computer system is capable of performing symmetrical multi-processing operations. More particularly, the dockable computer system includes a portable computer and a host station (docking station), each including a resident CPU. The dockable computer system is capable of operating in a docked state in which the portable computer is physically joined with the host station and an undocked state in which the portable computer is physically separate from the host station. In the docked state, the dockable computer system is capable of performing demanding computational tasks such as video conferencing as one of the CPUs in either the portable computer or host station is dedicated to the video conferencing operation. The dockable computer system preferably includes a communication channel for transmitting multi-processing support signals between the portable computer and the host station. Multi-processing support signals include synchronization signals, cache coherency signals, and interrupt distribution signals such as the LOCK signal, PLOCK signal, FLUSH signal, EADS signal, INTR signal or INTACK signal. The communication channel may be a dedicated bus or may be provided through a docking bridge between the portable computer and host station. The dockable computer system advantageously optimizes CPU resources when the dockable computer system is in a docked state.
摘要翻译： 可停靠的计算机系统能够执行对称的多处理操作。 更具体地，可停靠的计算机系统包括便携式计算机和主机站（对接站），每个都包括驻留的CPU。 可停靠的计算机系统能够在对接状态下操作，其中便携式计算机与主机站物理连接，并且其中便携式计算机在物理上与主机站分离的未停靠状态。 在对接状态下，可停靠的计算机系统能够执行诸如视频会议的苛刻的计算任务，因为便携式计算机或主机站中的一个CPU专用于视频会议操作。 对接计算机系统优选地包括用于在便携式计算机和主机站之间传送多处理支持信号的通信信道。 多处理支持信号包括同步信号，高速缓存一致性信号和中断分配信号，例如LOCK信号，PLOCK信号，FLUSH信号，EADS信号，INTR信号或INTACK信号。 通信信道可以是专用总线，或者可以通过便携式计算机和主机站之间的对接桥提供。 可对接计算机系统有利地优化当可停靠的计算机系统处于对接状态时的CPU资源。
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公开(公告)号：US5754190A
公开(公告)日：1998-05-19
申请号：US481630
申请日：1995-06-07
CPC分类号： G06T9/001
摘要： A method and apparatus for transferring original data which includes images, between two stations located a distance apart, without actual transmission of the image portion of the data. A library of images are provided at each of the stations. The image to be transferred is processed into a description of the image which allows the reproduction of the image at the receiving end of the transmission using the images contained in the image library in the receiving station.
摘要翻译： 一种用于传送原始数据的方法和装置，其中包括位于距离分开的两个站之间的图像，而不实际传输数据的图像部分。 每个电台都提供图像库。 要传送的图像被处理成图像的描述，其允许使用包含在接收站中的图像库中的图像在传输的接收端再现图像。
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公开(公告)号：US06499086B2
公开(公告)日：2002-12-24
申请号：US09770461
申请日：2001-01-29
IPC分类号： G06F1200
CPC分类号： G06F12/0875
摘要： A dedicated bus between a central processing unit and a peripheral unit, such as a graphics controller driving a video display, provides enhanced capability in an environment in which signal processing occurs within the central processing unit. The dedicated bus relieves other data buses, such as the PCI bus, of the need to communicate large amounts of data, such as decompressed video data. The resulting system supports high bandwidth transmissions of decompressed video data, enabling high resolution 24 bit full motion video and multiple data stream video.
摘要翻译： 在中央处理单元和周边单元之间的专用总线，例如驱动视频显示器的图形控制器，在中央处理单元内发生信号处理的环境中提供增强的能力。 专用总线减轻了诸如PCI总线的其他数据总线，需要传送大量数据，例如解压缩的视频数据。 所得到的系统支持解压缩视频数据的高带宽传输，实现高分辨率24位全动态视频和多数据流视频。
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5.发明授权System for dynamically reconfiguring subbusses of data bus according to system needs based on monitoring each of the information channels that make up data bus 失效根据系统需要动态重新配置数据总线子系统的系统，基于监控构成数据总线的每个信息通道
公开(公告)号：US5901332A
公开(公告)日：1999-05-04
申请号：US921078
申请日：1997-08-29
CPC分类号： G06F13/4018 , G06F13/385
摘要： A data bus for connecting information processing devices is configurable into a plurality of subbusses in order to fully utilize the data bus capacity. The size and data transfer direction of each subbus, as well as the data transfer speed of each subbus, is independent of the other subbusses. Also, the data bus can be reconfigured to meet changing system requirements. A data bus controller is thus provided to accomplish this data bus reconfiguration. The reconfiguration may be accomplished in accordance with one of a plurality of information flow templates which may be stored in a memory. A method of configuring a data bus is also provided wherein information transfer needs of a system are identified and the data bus is configured according to the identified information transfer means. The reconfiguration in accordance with the information transfer needs may be accomplished in accordance with one or more information flow templates which may be stored in a memory. The system may operate in accordance with a self arbitration scheme such that reconfiguration of the system is based on operational experience, such as utilization rates or excess capacity associated with each of the subbusses.
摘要翻译： 用于连接信息处理设备的数据总线可配置成多个子总线，以便充分利用数据总线容量。 每个子总线的大小和数据传输方向以及每个子总线的数据传输速度与其他子总线无关。 此外，数据总线可以重新配置以满足不断变化的系统要求。 因此提供数据总线控制器来完成该数据总线重新配置。 重新配置可以根据可存储在存储器中的多个信息流模板之一来完成。 还提供了一种配置数据总线的方法，其中识别系统的信息传送需求，并且根据所识别的信息传送装置配置数据总线。 根据信息传送需求的重新配置可以根据可存储在存储器中的一个或多个信息流模板来完成。 系统可以根据自我仲裁方案操作，使得系统的重新配置基于诸如与每个子总线相关联的利用率或过多容量的操作经验。
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公开(公告)号：US5734843A
公开(公告)日：1998-03-31
申请号：US476872
申请日：1995-06-07
CPC分类号： G06F13/36
摘要： A method of allocating bandwidth among a plurality of devices communicatively connected through a data bus provides for determining a data need of at least one of the plurality of devices, allocating portions of the data bus to the devices in response to the data need, and transmitting data between the devices on the allocated portions of the data bus. The portions of the data bus can be subbusses, each comprising at least one bit line. The data need can be based on a measure of fullness of a buffer corresponding to the at least one device. The data need can be provided as feedback from the buffer to a data bus controller which allocates the portions of the data bus. The method can use rules for assigning the subbusses which are stored in a memory. A processor can change the rules to accommodate changing conditions in the data bus. Also provided is a data communication system comprising a dynamically reconfigurable data bus, a data bus controller connected to the dynamically reconfigurable data bus for configuring subbusses of the data bus, a plurality of receiving devices connected to the data bus, and a feedback connection from at least one of the receiving devices to the data bus controller, wherein the data bus controller configures the subbusses in accordance with feedback received over the feedback connection. A memory can be connected to the data bus controller for storing rules for use by the data bus controller in configuring the subbusses. A processor can change the rules to accommodate changing conditions in the data bus.
摘要翻译： 在通过数据总线通信连接的多个设备之间分配带宽的方法提供用于确定多个设备中的至少一个设备的数据需求，响应于数据需要将数据总线的部分分配给设备，并且发送 在数据总线的分配部分上的设备之间的数据。 数据总线的部分可以是子总线，每个都包括至少一个位线。 数据需要可以基于对应于至少一个设备的缓冲器的丰满度的量度。 数据需求可以作为从缓冲器到分配数据总线部分的数据总线控制器的反馈来提供。 该方法可以使用用于分配存储在存储器中的子总线的规则。 处理器可以改变规则以适应数据总线中的变化条件。 还提供了一种数据通信系统，包括动态可重新配置的数据总线，连接到动态可重配置数据总线的数据总线控制器，用于配置数据总线的子总线，连接到数据总线的多个接收设备，以及来自 至少一个接收设备到达数据总线控制器，其中数据总线控制器根据通过反馈连接接收到的反馈来配置子总线。 存储器可以连接到数据总线控制器，用于存储数据总线控制器在配置子总线时使用的规则。 处理器可以改变规则以适应数据总线中的变化条件。
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公开(公告)号：US5615207A
公开(公告)日：1997-03-25
申请号：US482045
申请日：1995-06-07
IPC分类号： H04L12/46
CPC分类号： H04L12/4616
摘要： A data communication system includes an express bus, a plurality of local buses, and a plurality of local/express bridges, each local/express bridge connecting a corresponding local bus to the express bus. A plurality of local/local bridges each connect two corresponding local buses. The plurality of local buses and the plurality of local/local bridges comprise a local path. Also provided is a method of communicating information from a sending communication device to a target communication device, comprising the steps of a) determining if the target communication device is on a local bus corresponding to the sending communication device, b) transferring the information from the sending communication device to the target communication device on the local bus corresponding to the sending communication device if the result of step a) is that the target communication device is on the local bus corresponding to the sending communication device, c) transferring the information from the sending communication device to an express bus if the result of step a) is that the target communication device is not on the local bus corresponding to the sending communication device, d) transferring the information from the express bus to a local bus corresponding to the target communication device, and e) transferring the information from the local bus corresponding to the target communication device to the target communication device.
摘要翻译： 数据通信系统包括快速总线，多个本地总线和多个本地/快速桥接器，每个本地/快速桥接器将相应的本地总线连接到快速总线。 多个本地/本地桥接器每个连接两个相应的本地总线。 多个本地总线和多个本地/本地桥接器包括本地路径。 还提供了一种从发送通信设备向目标通信设备传送信息的方法，包括以下步骤：a）确定目标通信设备是否在与发送通信设备相对应的本地总线上，b）将信息从 如果步骤a）的结果是目标通信设备在与发送通信设备相对应的本地总线上，则将通信设备发送到与发送通信设备相对应的本地总线上的目标通信设备，c）将信息从 如果步骤a）的结果是目标通信设备不在与发送通信设备相对应的本地总线上，则将通信设备发送到快速总线，d）将信息从快速总线传送到与目标对应的本地总线 通信设备，以及e）从与ta相对应的本地总线传送信息 rget通信设备到目标通信设备。
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公开(公告)号：US08239603B2
公开(公告)日：2012-08-07
申请号：US11417391
申请日：2006-05-03
申请人： Drew J. Dutton , Alan D. Berenbaum , Raphael Weiss
发明人： Drew J. Dutton , Alan D. Berenbaum , Raphael Weiss
IPC分类号： G06F13/40
CPC分类号： G06F13/4027
摘要： A system including a serialized secondary bus architecture. The system may include an LPC bus, an I/O controller, a serialized secondary bus, and at least one slave device. The LPC bus may be connected to the I/O controller, and the at least one slave device may be connected to the I/O controller via the serialized secondary bus. The serialized secondary bus has a reduced pin count relative to the LPC bus. The I/O controller may receive bus transactions from the LPC bus. The I/O controller may translate and forward LPC bus transactions to the at least one device over the secondary bus. The I/O controller may include a processing unit. The processing unit may initiate bus transactions intended for the at least one slave device. The I/O controller may also include a bus arbitration unit. The bus arbitration unit may arbitrate ownership of the secondary bus between the processing unit and the LPC bus.
摘要翻译： 一种包括序列化二次总线架构的系统。 该系统可以包括LPC总线，I / O控制器，串行化辅助总线和至少一个从设备。 LPC总线可以连接到I / O控制器，并且至少一个从设备可以经由串行辅助总线连接到I / O控制器。 串行次级总线相对于LPC总线的引脚数量减少。 I / O控制器可以从LPC总线接收总线事务。 I / O控制器可以通过辅助总线将LPC总线事务转换和转发到至少一个设备。 I / O控制器可以包括处理单元。 处理单元可以启动用于至少一个从设备的总线事务。 I / O控制器还可以包括总线仲裁单元。 总线仲裁单元可以仲裁处理单元和LPC总线之间的辅助总线的所有权。
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9.发明授权Computer system which performs intelligent byte slicing on a multi-byte wide bus 失效在多字节宽总线上执行智能字节分片的计算机系统
公开(公告)号：US6047350A
公开(公告)日：2000-04-04
申请号：US989329
申请日：1997-12-11
IPC分类号： G06F13/36 , G06F13/368 , G06F13/372 , G06F13/40 , H04N21/238 , G06F13/38
CPC分类号： H04N21/238 , G06F13/36 , G06F13/368 , G06F13/372 , G06F13/4013 , G06F13/4022 , G06F13/4027
摘要： A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local system bus or expansion bus, such as the PCI bus, and may also include a dedicated real-time bus or multimedia bus. Various multimedia devices are coupled to one or more of the expansion bus and/or the multimedia bus. The computer system includes byte slicing logic coupled to one or more of the expansion bus and/or the multimedia bus which operates to allow different data streams to use different byte channels simultaneously. Thus the byte sliced multimedia bus allows different peripherals to share the bus simultaneously. The byte slicing logic thus may assign one data stream to a subset of the total byte lanes on the multimedia bus, and fill the unused byte lanes with another data stream. The computer system of the present invention thus provides much greater performance for real-time applications than prior systems.
摘要翻译： 针对实时应用程序进行了优化的计算机系统，提高了当前计算机体系结构的性能。 该系统包括标准本地系统总线或扩展总线，例如PCI总线，并且还可以包括专用实时总线或多媒体总线。 各种多媒体设备耦合到一个或多个扩展总线和/或多媒体总线。 计算机系统包括耦合到一个或多个扩展总线和/或多媒体总线的字节分片逻辑，其操作以允许不同的数据流同时使用不同的字节通道。 因此，字节分片多媒体总线允许不同的外设同时共享总线。 因此，字节分片逻辑可以将一个数据流分配给多媒体总线上的总字节通道的子集，并且用另一个数据流填充未使用的字节通道。 因此，本发明的计算机系统为实时应用提供比现有系统更大的性能。
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公开(公告)号：US5923887A
公开(公告)日：1999-07-13
申请号：US650570
申请日：1996-05-20
申请人： Drew J. Dutton
发明人： Drew J. Dutton
CPC分类号： G06F13/24
摘要： An improved programmable interrupt controller for use in a computer system including one or more interrupt service providers (ISPs), usually central processing units (CPUs). At least one CPU and a main memory system are coupled to a host bus. A bus bridge device couples the host bus to the expansion bus. At least one I/O device is coupled to the expansion bus and generates an interrupt request signal. The bus bridge and other bus devices may also generate interrupt request signals. A programmable interrupt controller receives the interrupt requests and provides processor interrupt signals as well as information regarding resource requirements necessary for servicing the interrupts to the one or more CPUs. The programmable interrupt controller also receives interrupt acknowledge signals from the one or more CPUs.
摘要翻译： 一种改进的可编程中断控制器，用于包括一个或多个中断服务提供商（ISP）的计算机系统，通常是中央处理单元（CPU）。 至少一个CPU和主存储器系统耦合到主机总线。 总线桥装置将主机总线耦合到扩展总线。 至少一个I / O设备被耦合到扩展总线并产生中断请求信号。 总线桥和其他总线设备也可能产生中断请求信号。 可编程中断控制器接收中断请求并提供处理器中断信号以及关于维护一个或多个CPU的中断所需的资源需求的信息。 可编程中断控制器还从一个或多个CPU接收中断确认信号。
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