公开(公告)号：US5754190A

公开(公告)日：1998-05-19

申请号：US481630

申请日：1995-06-07

Applicant: Drew J. Dutton ,  Douglas D. Gephardt ,  Steven L. Belt ,  Brett B. Stewart ,  Rita M. Wisor

Inventor： Drew J. Dutton ,  Douglas D. Gephardt ,  Steven L. Belt ,  Brett B. Stewart ,  Rita M. Wisor

IPC: G06T9/00 ,  G06T13/00

CPC classification number: G06T9/001

Abstract: A method and apparatus for transferring original data which includes images, between two stations located a distance apart, without actual transmission of the image portion of the data. A library of images are provided at each of the stations. The image to be transferred is processed into a description of the image which allows the reproduction of the image at the receiving end of the transmission using the images contained in the image library in the receiving station.

Abstract translation: 一种用于传送原始数据的方法和装置，其中包括位于距离分开的两个站之间的图像，而不实际传输数据的图像部分。 每个电台都提供图像库。 要传送的图像被处理成图像的描述，其允许使用包含在接收站中的图像库中的图像在传输的接收端再现图像。

公开(公告)号：US06219754B1

公开(公告)日：2001-04-17

申请号：US08994489

申请日：1997-12-19

Applicant: Steven L. Belt ,  Douglas D. Gephardt ,  Drew J. Dutton ,  Brett B. Stewart ,  Rita M. Wisor

Inventor： Steven L. Belt ,  Douglas D. Gephardt ,  Drew J. Dutton ,  Brett B. Stewart ,  Rita M. Wisor

IPC: G06F1200

CPC classification number: G06F12/0875

Abstract: A dedicated bus between a central processing unit and a peripheral unit, such as a graphics controller driving a video display, provides enhanced capability in an environment in which signal processing occurs within the central processing unit. The dedicated bus relieves other data buses, such as the PCI bus, of the need to communicate large amounts of data, such as decompressed video data. The resulting system supports high bandwidth transmissions of decompressed video data, enabling high resolution 24 bit full motion video and multiple data stream video.

Abstract translation: 在中央处理单元和周边单元之间的专用总线，例如驱动视频显示器的图形控制器，在中央处理单元内发生信号处理的环境中提供增强的能力。 专用总线减轻了诸如PCI总线的其他数据总线，需要传送大量数据，例如解压缩的视频数据。 所得到的系统支持解压缩视频数据的高带宽传输，实现高分辨率24位全动态视频和多数据流视频。

公开(公告)号：US5625829A

公开(公告)日：1997-04-29

申请号：US276250

申请日：1994-07-18

Applicant: Douglas D. Gephardt ,  Steven L. Belt ,  Drew J. Dutton

Inventor： Douglas D. Gephardt ,  Steven L. Belt ,  Drew J. Dutton

IPC: G06F15/173 ,  G06F1/16 ,  G06F13/36 ,  G06F13/364 ,  G06F13/40 ,  G06F3/00

CPC classification number: G06F13/364 ,  G06F1/1632 ,  G06F13/4036 ,  G06F13/4081

Abstract: A dockable computer system is capable of performing symmetrical multi-processing operations. More particularly, the dockable computer system includes a portable computer and a host station (docking station), each including a resident CPU. The dockable computer system is capable of operating in a docked state in which the portable computer is physically joined with the host station and an undocked state in which the portable computer is physically separate from the host station. In the docked state, the dockable computer system is capable of performing demanding computational tasks such as video conferencing as one of the CPUs in either the portable computer or host station is dedicated to the video conferencing operation. The dockable computer system preferably includes a communication channel for transmitting multi-processing support signals between the portable computer and the host station. Multi-processing support signals include synchronization signals, cache coherency signals, and interrupt distribution signals such as the LOCK signal, PLOCK signal, FLUSH signal, EADS signal, INTR signal or INTACK signal. The communication channel may be a dedicated bus or may be provided through a docking bridge between the portable computer and host station. The dockable computer system advantageously optimizes CPU resources when the dockable computer system is in a docked state.

Abstract translation: 可停靠的计算机系统能够执行对称的多处理操作。 更具体地，可停靠的计算机系统包括便携式计算机和主机站（对接站），每个都包括驻留的CPU。 可停靠的计算机系统能够在对接状态下操作，其中便携式计算机与主机站物理连接，并且其中便携式计算机在物理上与主机站分离的未停靠状态。 在对接状态下，可停靠的计算机系统能够执行诸如视频会议的苛刻的计算任务，因为便携式计算机或主机站中的一个CPU专用于视频会议操作。 对接计算机系统优选地包括用于在便携式计算机和主机站之间传送多处理支持信号的通信信道。 多处理支持信号包括同步信号，高速缓存一致性信号和中断分配信号，例如LOCK信号，PLOCK信号，FLUSH信号，EADS信号，INTR信号或INTACK信号。 通信信道可以是专用总线，或者可以通过便携式计算机和主机站之间的对接桥提供。 可对接计算机系统有利地优化当可停靠的计算机系统处于对接状态时的CPU资源。

公开(公告)号：US06499086B2

公开(公告)日：2002-12-24

申请号：US09770461

申请日：2001-01-29

Applicant: Steven L. Belt ,  Douglas D. Gephardt ,  Drew J. Dutton ,  Brett B. Stewart ,  Rita M. Wisor

Inventor： Steven L. Belt ,  Douglas D. Gephardt ,  Drew J. Dutton ,  Brett B. Stewart ,  Rita M. Wisor

IPC: G06F1200

CPC classification number: G06F12/0875

Abstract: A dedicated bus between a central processing unit and a peripheral unit, such as a graphics controller driving a video display, provides enhanced capability in an environment in which signal processing occurs within the central processing unit. The dedicated bus relieves other data buses, such as the PCI bus, of the need to communicate large amounts of data, such as decompressed video data. The resulting system supports high bandwidth transmissions of decompressed video data, enabling high resolution 24 bit full motion video and multiple data stream video.

Abstract translation: 在中央处理单元和周边单元之间的专用总线，例如驱动视频显示器的图形控制器，在中央处理单元内发生信号处理的环境中提供增强的能力。 专用总线减轻了诸如PCI总线的其他数据总线，需要传送大量数据，例如解压缩的视频数据。 所得到的系统支持解压缩视频数据的高带宽传输，实现高分辨率24位全动态视频和多数据流视频。

公开(公告)号：US5901332A

公开(公告)日：1999-05-04

申请号：US921078

申请日：1997-08-29

Applicant: Douglas D. Gephardt ,  Brett B. Stewart ,  Rita M. Wisor ,  Steven L. Belt ,  Drew J. Dutton

Inventor： Douglas D. Gephardt ,  Brett B. Stewart ,  Rita M. Wisor ,  Steven L. Belt ,  Drew J. Dutton

IPC: G06F13/38 ,  G06F13/40

CPC classification number: G06F13/4018 ,  G06F13/385

Abstract: A data bus for connecting information processing devices is configurable into a plurality of subbusses in order to fully utilize the data bus capacity. The size and data transfer direction of each subbus, as well as the data transfer speed of each subbus, is independent of the other subbusses. Also, the data bus can be reconfigured to meet changing system requirements. A data bus controller is thus provided to accomplish this data bus reconfiguration. The reconfiguration may be accomplished in accordance with one of a plurality of information flow templates which may be stored in a memory. A method of configuring a data bus is also provided wherein information transfer needs of a system are identified and the data bus is configured according to the identified information transfer means. The reconfiguration in accordance with the information transfer needs may be accomplished in accordance with one or more information flow templates which may be stored in a memory. The system may operate in accordance with a self arbitration scheme such that reconfiguration of the system is based on operational experience, such as utilization rates or excess capacity associated with each of the subbusses.

Abstract translation: 用于连接信息处理设备的数据总线可配置成多个子总线，以便充分利用数据总线容量。 每个子总线的大小和数据传输方向以及每个子总线的数据传输速度与其他子总线无关。 此外，数据总线可以重新配置以满足不断变化的系统要求。 因此提供数据总线控制器来完成该数据总线重新配置。 重新配置可以根据可存储在存储器中的多个信息流模板之一来完成。 还提供了一种配置数据总线的方法，其中识别系统的信息传送需求，并且根据所识别的信息传送装置配置数据总线。 根据信息传送需求的重新配置可以根据可存储在存储器中的一个或多个信息流模板来完成。 系统可以根据自我仲裁方案操作，使得系统的重新配置基于诸如与每个子总线相关联的利用率或过多容量的操作经验。

公开(公告)号：US5734843A

公开(公告)日：1998-03-31

申请号：US476872

申请日：1995-06-07

Applicant: Douglas D. Gephardt ,  Brett B. Stewart ,  Rita M. Wisor ,  Drew J. Dutton ,  Steven L. Belt

Inventor： Douglas D. Gephardt ,  Brett B. Stewart ,  Rita M. Wisor ,  Drew J. Dutton ,  Steven L. Belt

IPC: G06F13/36 ,  G06F13/00

CPC classification number: G06F13/36

Abstract: A method of allocating bandwidth among a plurality of devices communicatively connected through a data bus provides for determining a data need of at least one of the plurality of devices, allocating portions of the data bus to the devices in response to the data need, and transmitting data between the devices on the allocated portions of the data bus. The portions of the data bus can be subbusses, each comprising at least one bit line. The data need can be based on a measure of fullness of a buffer corresponding to the at least one device. The data need can be provided as feedback from the buffer to a data bus controller which allocates the portions of the data bus. The method can use rules for assigning the subbusses which are stored in a memory. A processor can change the rules to accommodate changing conditions in the data bus. Also provided is a data communication system comprising a dynamically reconfigurable data bus, a data bus controller connected to the dynamically reconfigurable data bus for configuring subbusses of the data bus, a plurality of receiving devices connected to the data bus, and a feedback connection from at least one of the receiving devices to the data bus controller, wherein the data bus controller configures the subbusses in accordance with feedback received over the feedback connection. A memory can be connected to the data bus controller for storing rules for use by the data bus controller in configuring the subbusses. A processor can change the rules to accommodate changing conditions in the data bus.

Abstract translation: 在通过数据总线通信连接的多个设备之间分配带宽的方法提供用于确定多个设备中的至少一个设备的数据需求，响应于数据需要将数据总线的部分分配给设备，并且发送 在数据总线的分配部分上的设备之间的数据。 数据总线的部分可以是子总线，每个都包括至少一个位线。 数据需要可以基于对应于至少一个设备的缓冲器的丰满度的量度。 数据需求可以作为从缓冲器到分配数据总线部分的数据总线控制器的反馈来提供。 该方法可以使用用于分配存储在存储器中的子总线的规则。 处理器可以改变规则以适应数据总线中的变化条件。 还提供了一种数据通信系统，包括动态可重新配置的数据总线，连接到动态可重配置数据总线的数据总线控制器，用于配置数据总线的子总线，连接到数据总线的多个接收设备，以及来自 至少一个接收设备到达数据总线控制器，其中数据总线控制器根据通过反馈连接接收到的反馈来配置子总线。 存储器可以连接到数据总线控制器，用于存储数据总线控制器在配置子总线时使用的规则。 处理器可以改变规则以适应数据总线中的变化条件。

公开(公告)号：US5615207A

公开(公告)日：1997-03-25

申请号：US482045

申请日：1995-06-07

Applicant: Douglas D. Gephardt ,  Brett B. Stewart ,  Rita M. Wisor ,  Drew J. Dutton ,  Steven L. Belt

Inventor： Douglas D. Gephardt ,  Brett B. Stewart ,  Rita M. Wisor ,  Drew J. Dutton ,  Steven L. Belt

IPC: H04L12/46

CPC classification number: H04L12/4616

Abstract: A data communication system includes an express bus, a plurality of local buses, and a plurality of local/express bridges, each local/express bridge connecting a corresponding local bus to the express bus. A plurality of local/local bridges each connect two corresponding local buses. The plurality of local buses and the plurality of local/local bridges comprise a local path. Also provided is a method of communicating information from a sending communication device to a target communication device, comprising the steps of a) determining if the target communication device is on a local bus corresponding to the sending communication device, b) transferring the information from the sending communication device to the target communication device on the local bus corresponding to the sending communication device if the result of step a) is that the target communication device is on the local bus corresponding to the sending communication device, c) transferring the information from the sending communication device to an express bus if the result of step a) is that the target communication device is not on the local bus corresponding to the sending communication device, d) transferring the information from the express bus to a local bus corresponding to the target communication device, and e) transferring the information from the local bus corresponding to the target communication device to the target communication device.

Abstract translation: 数据通信系统包括快速总线，多个本地总线和多个本地/快速桥接器，每个本地/快速桥接器将相应的本地总线连接到快速总线。 多个本地/本地桥接器每个连接两个相应的本地总线。 多个本地总线和多个本地/本地桥接器包括本地路径。 还提供了一种从发送通信设备向目标通信设备传送信息的方法，包括以下步骤：a）确定目标通信设备是否在与发送通信设备相对应的本地总线上，b）将信息从 如果步骤a）的结果是目标通信设备在与发送通信设备相对应的本地总线上，则将通信设备发送到与发送通信设备相对应的本地总线上的目标通信设备，c）将信息从 如果步骤a）的结果是目标通信设备不在与发送通信设备相对应的本地总线上，则将通信设备发送到快速总线，d）将信息从快速总线传送到与目标对应的本地总线 通信设备，以及e）从与ta相对应的本地总线传送信息 rget通信设备到目标通信设备。

公开(公告)号：US20120013795A1

公开(公告)日：2012-01-19

申请号：US13242635

申请日：2011-09-23

Applicant: Steven L. Belt ,  Andrew T. Sultenfuss

Inventor： Steven L. Belt ,  Andrew T. Sultenfuss

IPC: G06F1/32 ,  H04N7/01

CPC classification number: G06F1/3203 ,  G06F1/3293 ,  Y02D10/122 ,  Y02D50/20

Abstract: An information handling system includes a processing system, a low-power processing system, and a chipset. The processing system is configured to operate using a power system configured to power a shared resource of the processing system and a non-shared resource of the processing system, and to disable the non-shared resource during a reduced operating state of the processing system. The low-power processing system is configured to access the shared resource of the processing system during operation of the low-power processing system, wherein the operation of the low-power processing system is separate from the operation of the processing system. The chipset includes a processor of the processing system and operable to be enabled during operation of the processing system, wherein the processor is configured to be disabled during operation of the low-power processing system.

Abstract translation: 信息处理系统包括处理系统，低功率处理系统和芯片组。 处理系统被配置为使用被配置为为处理系统的共享资源和处理系统的非共享资源供电的电力系统来操作，并且在处理系统的减少的操作状态期间禁用非共享资源。 低功率处理系统被配置为在低功率处理系统的操作期间访问处理系统的共享资源，其中低功率处理系统的操作与处理系统的操作分离。 芯片组包括处理系统的处理器，并且可操作以在处理系统的操作期间启用，其中处理器被配置为在低功率处理系统的操作期间被禁用。

公开(公告)号：US5687381A

公开(公告)日：1997-11-11

申请号：US599603

申请日：1996-02-09

Applicant: Scott E. Swanstrom ,  David S. Christie ,  Steven L. Belt

Inventor： Scott E. Swanstrom ,  David S. Christie ,  Steven L. Belt

IPC: G06F13/24

CPC classification number: G06F13/24

Abstract: An interrupt polling unit included within a bus interface unit of a microprocessor is provided. The interrupt polling unit causes a periodic interrupt acknowledge bus transaction to occur. If an interrupt controller receiving the interrupt acknowledge bus transaction returns an interrupt vector indicative of an interrupt service routine, then the microprocessor executes the interrupt service routine. The number of interrupt acknowledge bus transactions associated with the interrupt is reduced from two to one, and the microprocessor effectively prefetches the interrupt service routine before the interrupt is actually signaled. In one embodiment, the interrupt polling unit causes an interrupt acknowledge bus transaction to occur at the expiration of a programmable time interval. Another embodiment of the interrupt polling unit causes an interrupt acknowledge bus transaction subsequent to the occurrence of a bus transaction programmed by the user.

Abstract translation: 提供了包括在微处理器的总线接口单元内的中断轮询单元。 中断轮询单元导致周期性中断确认总线事务发生。 如果接收到中断确认总线事务的中断控制器返回指示中断服务程序的中断向量，则微处理器执行中断服务程序。 与中断相关联的中断确认总线事务数量从两个减少到一个，并且微处理器在实际发出中断之前有效地预取中断服务程序。 在一个实施例中，中断轮询单元导致在可编程时间间隔期满时发生中断确认总线事务。 中断轮询单元的另一实施例在由用户编程的总线事务发生之后导致中断确认总线事务。

公开(公告)号：US5551033A

公开(公告)日：1996-08-27

申请号：US893432

申请日：1992-06-04

Applicant: Mark J. Foster ,  Saifuddin T. Fakhruddin ,  James L. Walker ,  Matthew B. Mendelow ,  Jiming Sun ,  Rodman S. Brahman ,  Michael P. Krau ,  Brian D. Willoughby ,  Michael D. Maddix ,  Steven L. Belt ,  Scott A. Hovey ,  Mark A. Ruthenbeck

Inventor： Mark J. Foster ,  Saifuddin T. Fakhruddin ,  James L. Walker ,  Matthew B. Mendelow ,  Jiming Sun ,  Rodman S. Brahman ,  Michael P. Krau ,  Brian D. Willoughby ,  Michael D. Maddix ,  Steven L. Belt ,  Scott A. Hovey ,  Mark A. Ruthenbeck

IPC: G06F1/24 ,  G06F1/32 ,  G06F9/46 ,  G06F9/48 ,  G06F11/14 ,  G06F1/00 ,  G06F13/24

CPC classification number: G06F9/4812 ,  G06F1/24 ,  G06F1/3203 ,  G06F1/324 ,  G06F9/463 ,  Y02B60/1217 ,  Y02B60/144

Abstract: A laptop computer system includes a protected mode microprocessor capable of operating in restricted and unrestricted modes, and an arrangement which in response to a predetermined condition saves information from the processor and then forcibly switches the processor to its unrestricted mode of operation. The system includes a first interrupt mask register having a bit for indicating whether an interrupt is to be recognized by the processor, a second interrupt mask register having a bit for indicating whether the interrupt is to be recognized by a further circuit, and an arrangement responsive to a load of the first mask register for conforming the bit of the second mask register to the bit of the first mask register in a manner invisible to an application program being executed by the processor.

Abstract translation: 膝上型计算机系统包括能够以受限制和无限制模式操作的保护模式微处理器，并且响应于预定条件的装置保存来自处理器的信息，然后强制地将处理器切换到其无限制操作模式。 该系统包括第一中断屏蔽寄存器，该第一中断屏蔽寄存器具有用于指示处理器是否识别中断的位;第二中断屏蔽寄存器，具有用于指示该中断是否被另一电路识别的位，以及响应于 到第一掩模寄存器的负载，用于使第二掩模寄存器的位与第一掩模寄存器的位以对于由处理器执行的应用程序不可见的方式进行匹配。