公开(公告)号：US4858116A

公开(公告)日：1989-08-15

申请号：US44954

申请日：1987-05-01

申请人： Richard B. Gillett, Jr. ,  Douglas D. Williams

发明人： Richard B. Gillett, Jr. ,  Douglas D. Williams

IPC分类号： G06F15/16 ,  G06F9/46 ,  G06F9/52 ,  G06F12/00 ,  G06F13/42 ,  G06F15/177

CPC分类号： G06F9/52 ,  G06F13/4217 ,  G06F9/3004 ,  G06F9/30087

摘要： A computer system having multiple processors interconnected by a pended bus provides exclusive read-modify-write operations employing multiple lock bits. A processor generates an interlock read command which is transmitted as a transfer over the pended bus to a memory or I/O node. Acknowledge confirmations are transmitted by the memory back to the processor two bus cycles after each bus cycle of the processor transfer. The processor transfer, including an interlock read command, is stored in a input queue in memory and processes in turn by the memory. A first interlock read command to a specified memory location causes a lock bit to be set for that location and a first type of response message including the contents of the specified location to be generated by the memory and stored in an output queue. The memory obtains access to the pended bus through an arbitration process and transmits a response message including the contents of the memory location specified in the interlock read command at an unspecified time after initiation of the interlock read command. A subsequent interlock read command from the processor to the same memory location will result in a denial of access to the specified location and in the generation of a second type of response message by the memory which indicates that the specified location is locked.

摘要翻译： 具有通过挂起总线互连的多个处理器的计算机系统提供采用多个锁定位的独占读取 - 修改 - 写入操作。 处理器产生互锁读命令，该命令作为通过挂起总线的传送被传送到存储器或I / O节点。 在处理器传输的每个总线周期之后，确认确认由存储器发送回处理器两个总线周期。 处理器传输（包括互锁读取命令）存储在存储器中的输入队列中，并依次由存储器进行处理。 对指定的存储器位置的第一联锁读取命令导致为该位置设置锁定位，以及包括要由存储器生成并存储在输出队列中的指定位置的内容的第一类型的响应消息。 存储器通过仲裁处理获得对待处理总线的访问，并且在启动互锁读取命令之后的未指定时间发送包括在联锁读取命令中指定的存储器位置的内容的响应消息。 从处理器到相同存储器位置的随后的互锁读取命令将导致拒绝对指定位置的访问以及存储器生成指示指定位置被锁定的第二类型的响应消息。

公开(公告)号：US5430888A

公开(公告)日：1995-07-04

申请号：US143509

申请日：1993-10-26

申请人： Richard T. Witek ,  Douglas D. Williams ,  Timothy J. Stanley ,  David M. Fenwick ,  Douglas J. Burns ,  Rebecca L. Stamm ,  Richard Heye

发明人： Richard T. Witek ,  Douglas D. Williams ,  Timothy J. Stanley ,  David M. Fenwick ,  Douglas J. Burns ,  Rebecca L. Stamm ,  Richard Heye

IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F15/78 ,  G06F17/16

CPC分类号： G06F15/8069 ,  G06F12/0859 ,  G06F15/8084 ,  G06F9/383

摘要： A load/store pipeline in a computer processor for loading data to registers and storing data from the registers has a cache memory within the pipeline for storing data. The pipeline includes buffers which support multiple outstanding read request misses. Data from out of the pipeline is obtained independently of the operation of the pipeline, this data corresponding to the request misses. The cache memory can then be filled with the requested for data. The provision of a cache memory within the pipeline, and the buffers for supporting the cache memory, speed up loading operations for the computer processor.

摘要翻译： 用于将数据加载到寄存器和从寄存器存储数据的计算机处理器中的加载/存储管线具有用于存储数据的流水线内的高速缓冲存储器。 流水线包括支持多个未完成读请求未命中的缓冲区。 来自流水线的数据是独立于流水线的操作获取的，该数据对应于请求未命中。 然后可以用所请求的数据填充高速缓存存储器。 在流水线内提供高速缓冲存储器，以及用于支持高速缓冲存储器的缓冲器，加速计算机处理器的加载操作。

公开(公告)号：US5428794A

公开(公告)日：1995-06-27

申请号：US206109

申请日：1994-03-03

申请人： Douglas D. Williams

发明人： Douglas D. Williams

IPC分类号： G06F13/24 ,  G06F15/17 ,  G06F12/00 ,  G06F13/364 ,  G06F13/38

CPC分类号： G06F15/17 ,  G06F13/24

摘要： An interrupting node for providing interrupt requests to a pended bus. The interrupting node provides to the pended bus an interrupt request message including ID data for identifying the interrupting node as the source of an interrupt request. An interrupt servicing node provides interrupt acknowledge messages including destination data specifying a particular interrupting node at times when the interrupt servicing node is ready to service an interrupt request message. The interrupting node detects whether an interrupt acknowledge message on the bus includes destination data specifying that interrupting node, and provides an interrupt vector message to the bus in response.

摘要翻译： 用于向挂起总线提供中断请求的中断节点。 中断节点向挂起总线提供包括用于识别中断节点作为中断请求的源的ID数据的中断请求消息。 当中断服务节点准备好服务中断请求消息时，中断服务节点提供中断确认消息，包括指定特定中断节点的目标数据。 中断节点检测总线上的中断确认消息是否包含指定中断节点的目标数据，并响应中断向量消息给总线。

公开(公告)号：US5148536A

公开(公告)日：1992-09-15

申请号：US224483

申请日：1988-07-25

申请人： Richard T. Witek ,  Douglas D. Williams ,  Timothy J. Stanley ,  David M. Fenwick ,  Douglas J. Burns ,  Rebecca L. Stamm ,  Richard Heye

发明人： Richard T. Witek ,  Douglas D. Williams ,  Timothy J. Stanley ,  David M. Fenwick ,  Douglas J. Burns ,  Rebecca L. Stamm ,  Richard Heye

IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F15/78 ,  G06F17/16

CPC分类号： G06F15/8069 ,  G06F12/0859 ,  G06F15/8084 ,  G06F9/383

摘要： A load/store pipeline in a computer processor for loading data to registers and storing data from the registers has a cache memory within the pipeline for storing data. The pipeline includes buffers which support multiple outstanding read request misses. Data from out of the pipeline is obtained independently of the operation of the pipeline, this data corresponding to the request misses. The cache memory can then be filled with the data that has been requested. The provision of a cache memory within the pipeline, and the buffers for supporting the cache memory, speed up loading operations for the computer processor.

公开(公告)号：US5319791A

公开(公告)日：1994-06-07

申请号：US943165

申请日：1992-09-10

申请人： Douglas D. Williams ,  David M. Fenwick ,  Timothy J. Stanley

发明人： Douglas D. Williams ,  David M. Fenwick ,  Timothy J. Stanley

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F17/16 ,  G06F9/30 ,  G06F9/00

CPC分类号： G06F12/10 ,  G06F2212/655

摘要： A prediction logic device operating in conjunction with a vector processor to predict, before the completion of the translation of the virtual addresses of all of the data elements of a vector, the valid performance of all virtual-address to physical-address translations for the data elements of the vector. The prediction logic device asserts an MMOK signal to a scalar processor when it becomes known that no memory management fault and/or translation buffer miss will occur such that the scalar processor can resume vector instruction issue to the vector processor at the earliest possible time.

摘要翻译： 一种与矢量处理器结合操作的预测逻辑设备，用于在完成向量的所有数据元素的虚拟地址的翻译之前预测数据的所有虚拟地址到物理地址转换的有效性能 元素的向量。 当知道没有存储器管理故障和/或转换缓冲器丢失将发生时，预测逻辑器件向标量处理器断言MMOK信号，使得标量处理器可以在尽可能早的时间向向量处理器恢复向量指令发布。

公开(公告)号：US4941083A

公开(公告)日：1990-07-10

申请号：US44486

申请日：1987-05-01

申请人： Richard B. Gillett, Jr. ,  Douglas D. Williams

发明人： Richard B. Gillett, Jr. ,  Douglas D. Williams

IPC分类号： G06F15/16 ,  G06F9/46 ,  G06F9/52 ,  G06F13/366 ,  G06F13/42 ,  G06F15/177

CPC分类号： G06F9/466 ,  G06F13/4217

摘要： A processor node providing exclusive read-modify-write operations in a computer system having multiple processors interconnected by a pended bus and employing multiple lock bits. The processor generates an interlock read command which is transmitted as a transfer over the pended bus to a memory or I/O mode. Acknowledge confirmations are transmitted by the memory back to the processor two bus cycles after each bus cycle of the command transfer. The command transfer, including an interlock read command, is stored in an input queue in memory and is processed in turn by the memory. A first interlock read command to a specified memory location causes a lock bit to be set for that location and a first type of response message including the contents of the specified location to be generated by the memory and stored in an output queue. The memory obtains access to the pended bus through an arbitration process and transmits a response message including the contents of the memory location specified in the interlock read command at an unspecified time after initiation of the interlock read command. A subsequent interlock read command from the processor to the same memory location will result in a denial of access to the specified location and in the generation of a second type of response message by the memory which indicates that the specified location is locked.

摘要翻译： 处理器节点在具有多个处理器的计算机系统中提供排他性的读 - 修改 - 写入操作，所述多个处理器通过挂起总线互连并采用多个锁定位。 处理器产生互锁读取命令，该命令作为通过挂起总线的传输被传送到存储器或I / O模式。 在命令传输的每个总线周期之后，确认确认将由存储器发送回处理器两个总线周期。 包括联锁读取命令的命令传输存储在存储器中的输入队列中，并被存储器依次处理。 对指定的存储器位置的第一联锁读取命令导致为该位置设置锁定位，以及包括要由存储器生成并存储在输出队列中的指定位置的内容的第一类型的响应消息。 存储器通过仲裁处理获得对待处理总线的访问，并且在启动互锁读取命令之后的未指定时间发送包括在联锁读取命令中指定的存储器位置的内容的响应消息。 从处理器到相同存储器位置的随后的互锁读取命令将导致拒绝对指定位置的访问以及存储器生成指示指定位置被锁定的第二类型的响应消息。

公开(公告)号：US4774422A

公开(公告)日：1988-09-27

申请号：US44780

申请日：1987-05-01

申请人： Darrel D. Donaldson ,  Richard B. Gillett, Jr. ,  Douglas D. Williams

发明人： Darrel D. Donaldson ,  Richard B. Gillett, Jr. ,  Douglas D. Williams

IPC分类号： G06F3/00 ,  G06F13/40 ,  H03K17/16 ,  H03K19/017 ,  H03K19/092

CPC分类号： G06F13/4072

摘要： Bus interface apparatus is provided to drive a high speed bus with two nonoverlapping clock signals. The apparatus takes advantage of the inherent bus capacitance which will temporarily hold data signals placed on the bus by using bus interface circuitry having high input and output impedances. That circuitry can thus be activated by coincident signals.

摘要翻译： 提供总线接口装置以驱动具有两个不重叠时钟信号的高速总线。 该装置利用通过使用具有高输入和输出阻抗的总线接口电路临时保持放置在总线上的数据信号的固有总线电容。 因此，可以通过重合的信号激活该电路。

公开(公告)号：US5068781A

公开(公告)日：1991-11-26

申请号：US372565

申请日：1989-06-28

申请人： Richard B. Gillett, Jr. ,  Douglas D. Williams

发明人： Richard B. Gillett, Jr. ,  Douglas D. Williams

IPC分类号： G06F9/46 ,  G06F13/42

CPC分类号： G06F9/52 ,  G06F13/4217

摘要： A computer system having multiple processors interconnected by a pended bus provides exclusive read-modify-write operations employing multiple lock bits. A processor generates an interlock read command which is transmitted as a transfer over the pended bus to a memory or I/O node. Acknowledge confirmations are transmitted by the memory back to the processor two bus cycles after each bus cycle of the processor transfer. The processor transfer, including an interlock read command, is stored in a input queue in memory and processes in turn by the memory. A first interlock read command to a specified memory location causes a lock bit to be set for that location and a first type of response message including the contents of the specified location to be generated by the memory and stored in an output queue. The memory obtains access to the pended bus through an arbitration process and transmits a response message including the contents of the memory location specified in the interlock read command at an unspecified time after initiation of the interlock read command. A subsequent interlock read command from the processor to the same memory location will result in a denial of access to the specified location and in the generation of a second type of response message by the memory which indicates that the specified location is locked.

摘要翻译： 具有通过挂起总线互连的多个处理器的计算机系统提供采用多个锁定位的独占读取 - 修改 - 写入操作。 处理器产生互锁读命令，该命令作为通过挂起总线的传送被传送到存储器或I / O节点。 在处理器传输的每个总线周期之后，确认确认由存储器发送回处理器两个总线周期。 处理器传输（包括互锁读取命令）存储在存储器中的输入队列中，并依次由存储器进行处理。 对指定的存储器位置的第一联锁读取命令导致为该位置设置锁定位，以及包括要由存储器生成并存储在输出队列中的指定位置的内容的第一类型的响应消息。 存储器通过仲裁处理获得对待处理总线的访问，并且在启动互锁读取命令之后的未指定时间发送包括在联锁读取命令中指定的存储器位置的内容的响应消息。 从处理器到相同存储器位置的随后的互锁读取命令将导致拒绝对指定位置的访问以及存储器生成指示指定位置被锁定的第二类型的响应消息。

公开(公告)号：US4953072A

公开(公告)日：1990-08-28

申请号：US44755

申请日：1987-05-01

申请人： Douglas D. Williams

发明人： Douglas D. Williams

IPC分类号： G06F13/24 ,  G06F15/17

CPC分类号： G06F13/24 ,  G06F15/17

摘要： Interrupt servicing node for servicing interrupt requests on a pended bus. The interrupt servicing node provides interrupt acknowledge messages including destination data specifying a particular interrupting node at times when the interrupt servicing node is ready to service the interrupt request message. The interrupt servicing node includes storage elements for indicating whether an interrupt request is pending from a particular interrupting node. An interrupt request message on the bus includes ID data for identifying a particular interrupting node as the source of an interrupt request.

摘要翻译： 中断服务节点，用于在挂起总线上维护中断请求。 当中断服务节点准备好服务中断请求消息时，中断服务节点提供中断确认消息，包括指定特定中断节点的目标数据。 中断服务节点包括用于指示来自特定中断节点的中断请求是否正在等待的存储元件。 总线上的中断请求消息包括用于识别特定中断节点作为中断请求源的ID数据。

公开(公告)号：US4829515A

公开(公告)日：1989-05-09

申请号：US44467

申请日：1987-05-01

申请人： Darrel D. Donaldson ,  Richard B. Gillett, Jr. ,  Douglas D. Williams

发明人： Darrel D. Donaldson ,  Richard B. Gillett, Jr. ,  Douglas D. Williams

IPC分类号： G06F13/36 ,  G06F13/40

CPC分类号： G06F13/4027

摘要： An interface system between a high speed user bus and a system bus is provided to present to the user bus a picture of the data transferred on the system bus every clock cycle of that system bus. The interface system also allows the user bus to transfer data back to the system bus during selected bus cycles. By using a single pin connection to the system bus, the user bus can send communications back to itself by way of the system bus.

摘要翻译： 提供高速用户总线和系统总线之间的接口系统，以便在系统总线的每个时钟周期向用户总线呈现在系统总线上传送的数据的图像。 接口系统还允许用户总线在选择的总线周期期间将数据传送回系统总线。 通过使用与系统总线的单引脚连接，用户总线可以通过系统总线将通信发送回自身。