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    MINIMIZING LEAKAGE CURRENT AND JUNCTION CAPACITANCE IN CMOS TRANSISTORS BY UTILIZING DIELECTRIC SPACERS
    1.
    发明申请
    MINIMIZING LEAKAGE CURRENT AND JUNCTION CAPACITANCE IN CMOS TRANSISTORS BY UTILIZING DIELECTRIC SPACERS 失效
    通过使用电介质间隔来最小化CMOS晶体管的漏电流和结电容

    公开(公告)号：US20120261672A1

    公开(公告)日：2012-10-18

    申请号：US13084594

    申请日：2011-04-12

    申请人： Dureseti Chidambarrao ,  Ramachandran Muralidhar ,  Philip J. Oldiges ,  Viorel Ontalus

    发明人： Dureseti Chidambarrao ,  Ramachandran Muralidhar ,  Philip J. Oldiges ,  Viorel Ontalus

    IPC分类号： H01L27/092 ,  H01L21/782 ,  H01L21/8238 ,  H01L27/12

    CPC分类号： H01L21/823814 ,  H01L21/3086 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823864 ,  H01L21/84

    摘要： A semiconductor structure and method for forming dielectric spacers and epitaxial layers for a complementary metal-oxide-semiconductor field effect transistor (CMOS transistor) are disclosed. Specifically, the structure and method involves forming dielectric spacers that are disposed in trenches and are adjacent to the silicon substrate, which minimizes leakage current. Furthermore, epitaxial layers are deposited to form source and drain regions, wherein the source region and drain regions are spaced at a distance from each other. The epitaxial layers are disposed adjacent to the dielectric spacers and the transistor body regions (i.e., portion of substrate below the gates), which can minimize transistor junction capacitance. Minimizing transistor junction capacitance can enhance the switching speed of the CMOS transistor. Accordingly, the application of dielectric spacers and epitaxial layers to minimize leakage current and transistor junction capacitance in CMOS transistors can enhance the utility and performance of the CMOS transistors in low power applications.

    摘要翻译： 公开了用于形成用于互补金属氧化物半导体场效应晶体管（CMOS晶体管）的电介质间隔物和外延层的半导体结构和方法。 具体地，该结构和方法包括形成设置在沟槽中并且与硅衬底相邻的电介质间隔物，这使漏电流最小化。 此外，沉积外延层以形成源极和漏极区域，其中源极区域和漏极区域彼此间隔一定距离。 外延层邻近电介质间隔物和晶体管本体区域（即，栅极下方的衬底部分）设置，这可使晶体管结电容最小化。 最小化晶体管结电容可以提高CMOS晶体管的开关速度。 因此，应用介电间隔物和外延层以最小化CMOS晶体管中的漏电流和晶体管结电容可以增强低功率应用中CMOS晶体管的效用和性能。

    Gate structures and methods of manufacture
    5.
    发明授权
    Gate structures and methods of manufacture 有权
    门结构和制造方法

    公开(公告)号：US08895384B2

    公开(公告)日：2014-11-25

    申请号：US13293210

    申请日：2011-11-10

    申请人： Unoh Kwon ,  Ramachandran Muralidhar ,  Viorel Ontalus

    发明人： Unoh Kwon ,  Ramachandran Muralidhar ,  Viorel Ontalus

    IPC分类号： H01L21/8238 ,  H01L21/8234

    CPC分类号： H01L27/0922 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/42364

    摘要： A metal gate structure with a channel material and methods of manufacture such structure is provided. The method includes forming dummy gate structures on a substrate. The method further includes forming sidewall structures on sidewalls of the dummy gate structures. The method further includes removing the dummy gate structures to form a first trench and a second trench, defined by the sidewall structures. The method further includes forming a channel material on the substrate in the first trench and in the second trench. The method further includes removing the channel material from the second trench while the first trench is masked. The method further includes filling remaining portions of the first trench and the second trench with gate material.

    摘要翻译： 提供了具有通道材料的金属栅极结构及其制造方法。 该方法包括在衬底上形成虚拟栅极结构。 该方法还包括在虚拟栅极结构的侧壁上形成侧壁结构。 该方法还包括去除伪栅极结构以形成由侧壁结构限定的第一沟槽和第二沟槽。 该方法还包括在第一沟槽和第二沟槽中的衬底上形成沟道材料。 该方法还包括在第一沟槽被掩蔽的同时从第二沟槽去除沟道材料。 该方法还包括用栅极材料填充第一沟槽和第二沟槽的剩余部分。

    FORMING CMOS WITH CLOSE PROXIMITY STRESSORS
    6.
    发明申请
    FORMING CMOS WITH CLOSE PROXIMITY STRESSORS 有权
    形成具有紧密接近压力的CMOS

    公开(公告)号：US20130295740A1

    公开(公告)日：2013-11-07

    申请号：US13465159

    申请日：2012-05-07

    申请人： Desmond J. Donegan, JR. ,  Abhishek Dube ,  Steven Jones ,  JOPHY S. KOSHY ,  Viorel Ontalus

    发明人： Desmond J. Donegan, JR. ,  Abhishek Dube ,  Steven Jones ,  JOPHY S. KOSHY ,  Viorel Ontalus

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66628 ,  H01L29/66636

    摘要： A method of forming transistors with close proximity stressors to channel regions of the transistors is provided. The method includes forming a first transistor, in a first region of a substrate, having a gate stack on top of the first region of the substrate and a set of spacers adjacent to sidewalls of the gate stack, the first region including a source and drain region of the first transistor; forming a second transistor, in a second region of the substrate, having a gate stack on top of the second region of the substrate and a set of spacers adjacent to sidewalls of the gate stack, the second region including a source and drain region of the second transistor; covering the first transistor with a photo-resist mask without covering the second transistor; creating recesses in the source and drain regions of the second transistor; and forming stressors in the recesses.

    摘要翻译： 提供了一种形成具有接近应力的晶体管到晶体管的沟道区域的方法。 该方法包括在衬底的第一区域中形成第一晶体管，在衬底的第一区域的顶部上具有栅极叠层，以及邻近栅堆叠的侧壁的一组间隔物，第一区域包括源极和漏极 第一晶体管的区域; 在所述衬底的第二区域中形成第二晶体管，在所述衬底的所述第二区域的顶部上具有栅极叠层，以及邻近所述栅极叠层的侧壁的一组间隔区，所述第二区域包括所述栅极叠层的源极和漏极区域 第二晶体管; 用光致抗蚀剂掩模覆盖第一晶体管而不覆盖第二晶体管; 在所述第二晶体管的源极和漏极区域中产生凹陷; 并在凹槽中形成应力源。

    Methods of fabricating optimization involving process sequence analysis
    7.
    发明授权
    Methods of fabricating optimization involving process sequence analysis 失效
    制造优化涉及过程序列分析的方法

    公开(公告)号：US07502658B1

    公开(公告)日：2009-03-10

    申请号：US12033502

    申请日：2008-02-19

    申请人： Steven G. Barbee ,  Jeong W. Nam ,  Viorel Ontalus ,  Yuusheng Song

    发明人： Steven G. Barbee ,  Jeong W. Nam ,  Viorel Ontalus ,  Yuusheng Song

    IPC分类号： G06F19/00

    CPC分类号： G05B19/41865 ,  G05B2219/32191 ,  G05B2219/32204 ,  G05B2219/32291 ,  G05B2219/32324 ,  G05B2219/45031 ,  Y02P90/20 ,  Y02P90/22

    摘要： An exemplary method for performing fabrication sequence analysis, the method comprising, defining a process group, wherein a process group includes fabrication processes in a fabrication sequence, determining fabrication process paths in the process group to define independent variables, wherein a process path is a plurality of fabrication equipment used to fabricate a particular semiconductor device in the fabrication sequence, receiving a dependent variable for the fabrication sequence, performing analysis of variance to calculate a p-value for the process group, determining whether the p-value is lower than a threshold value, identifying a poor process path responsive to determining that the p-value is lower than a threshold value, and outputting the identified poor process path.

    摘要翻译： 一种用于执行制造序列分析的示例性方法，所述方法包括：定义过程组，其中过程组包括制造序列中的制造过程，确定所述过程组中的制造过程路径以定义独立变量，其中过程路径是多个 用于在制造序列中制造特定半导体器件的制造设备，接收制造序列的因变量，执行方差分析以计算过程组的p值，确定p值是否低于阈值 值，识别响应于确定所述p值低于阈值的差的处理路径，以及输出所识别的不良处理路径。

    PERFORMANCE AND REDUCING VARIATION OF NARROW CHANNEL DEVICES
    8.
    发明申请
    PERFORMANCE AND REDUCING VARIATION OF NARROW CHANNEL DEVICES 有权
    性能和减少NARROW通道设备的变化

    公开(公告)号：US20130095619A1

    公开(公告)日：2013-04-18

    申请号：US13272340

    申请日：2011-10-13

    申请人： Deepal Wehella-Gamage ,  Viorel Ontalus

    发明人： Deepal Wehella-Gamage ,  Viorel Ontalus

    IPC分类号： H01L21/84 ,  H01L21/336

    CPC分类号： H01L29/66636 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7848

    摘要： Embodiment of the present invention provides a method of forming transistors such as narrow channel transistors. The method includes creating a transistor region in a substrate; the transistor region being separated from rest of the substrate, by one or more shallow trench isolation (STI) regions formed in the substrate, to include a channel region, a source region, and a drain region; the STI regions having a height higher than the transistor region of the substrate; and the channel region having a gate stack on top thereof; forming spacers at sidewalls of the STI regions above the transistor region; creating recesses in the source region and the drain region with the spacers preserving at least a portion of material of the substrate underneath the spacers along sidewalls of the STI regions; and epitaxially growing source and drain of the transistor in the recesses.

    摘要翻译： 本发明的实施例提供了一种形成诸如窄沟道晶体管的晶体管的方法。 该方法包括在衬底中形成晶体管区域; 所述晶体管区域通过在所述衬底中形成的一个或多个浅沟槽隔离（STI）区域与所述衬底的其余部分分离，以包括沟道区域，源极区域和漏极区域; 所述STI区域具有高于所述衬底的晶体管区域的高度; 并且所述沟道区在其顶部具有栅极堆叠; 在晶体管区域上方的STI区域的侧壁处形成间隔物; 在所述源区域和所述漏极区域中产生凹槽，所述间隔物在所述STI区域的侧壁处保留所述衬垫下方的所述衬底的材料的至少一部分; 并且在凹槽中外延生长晶体管的源极和漏极。

    Cavity-free interface between extension regions and embedded silicon-carbon alloy source/drain regions
    9.
    发明授权
    Cavity-free interface between extension regions and embedded silicon-carbon alloy source/drain regions 有权
    扩展区域和嵌入式硅 - 碳合金源极/漏极区域之间的无空隙界面

    公开(公告)号：US08394712B2

    公开(公告)日：2013-03-12

    申请号：US13101260

    申请日：2011-05-05

    申请人： Abhishek Dube ,  Viorel Ontalus

    发明人： Abhishek Dube ,  Viorel Ontalus

    IPC分类号： H01L21/20

    CPC分类号： H01L21/823481 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

    摘要： A gate stack is formed on a silicon substrate, and source/drain extension regions are formed around the gate stack. A dielectric spacer is formed around the gate stack. A pair of trenches is formed around the gate stack and the dielectric spacer by an etch so that sidewalls of the source/drain extension regions are exposed. Within each trench, an n-doped silicon liner is deposited on the sidewalls of the trenches by a first selective epitaxy process so that the interface between the dielectric spacer and the source/drain extension region is covered. Within each trench, an n-doped single crystalline silicon-carbon alloy is subsequently deposited to fill the trench by a second selective epitaxy process. A combination of an n-doped single crystalline silicon liner and an n-doped single crystalline silicon-carbon alloy functions as embedded source/drain regions of an n-type field effect transistor (NFET), which applies a tensile stress to the channel of the transistor.

    摘要翻译： 在硅衬底上形成栅极叠层，并且在栅极堆叠周围形成源极/漏极延伸区域。 在栅极堆叠周围形成介电隔离物。 通过蚀刻在栅极堆叠和电介质间隔物周围形成一对沟槽，使得源极/漏极延伸区域的侧壁被暴露。 在每个沟槽内，通过第一选择性外延工艺将n掺杂硅衬垫沉积在沟槽的侧壁上，以便覆盖介质间隔物与源极/漏极延伸区之间的界面。 在每个沟槽内，随后沉积n掺杂的单晶硅 - 碳合金以通过第二选择性外延工艺填充沟槽。 n掺杂单晶硅衬垫和n掺杂单晶硅碳合金的组合用作n型场效应晶体管（NFET）的嵌入式源极/漏极区域，其对该沟道施加拉伸应力 晶体管。

    REDUCED PATTERN LOADING FOR DOPED EPITAXIAL PROCESS AND SEMICONDUCTOR STRUCTURE
    10.
    发明申请
    REDUCED PATTERN LOADING FOR DOPED EPITAXIAL PROCESS AND SEMICONDUCTOR STRUCTURE 失效
    用于掺杂外延工艺和半导体结构的减少图案加载

    公开(公告)号：US20120248436A1

    公开(公告)日：2012-10-04

    申请号：US13075450

    申请日：2011-03-30

    申请人： Abhishek Dube ,  Viorel Ontalus ,  Kathryn T. Schonenberg ,  Zhengmao Zhu

    发明人： Abhishek Dube ,  Viorel Ontalus ,  Kathryn T. Schonenberg ,  Zhengmao Zhu

    IPC分类号： H01L23/48 ,  H01L21/20

    CPC分类号： H01L21/823425 ,  H01L21/02529 ,  H01L21/02576 ,  H01L21/823412 ,  H01L22/12 ,  H01L22/34 ,  H01L29/66636 ,  H01L29/7848

    摘要： A semiconductor substrate having transistor structures and test structures with spacing between the transistor structures smaller than the spacing between the test structures is provided. A first iteratively performed deposition and etch process includes: depositing a first doped epitaxial layer having a first concentration of a dopant over the semiconductor substrate, and etching the first doped epitaxial layer. A second iteratively performed deposition and etch process includes: depositing a second doped epitaxial layer having a second concentration of the dopant higher than the first concentration over the semiconductor substrate, and etching the second doped epitaxial layer. The first concentration results in a first net growth rate over the transistor structures and the second concentration results in a lower, second net growth rate over the test structures than the transistor structures, resulting in reduced pattern loading.

    摘要翻译： 提供了具有晶体管结构的半导体衬底和在晶体管结构之间具有小于测试结构之间的间隔的测试结构。 第一迭代执行的沉积和蚀刻工艺包括：在半导体衬底上沉积具有掺杂剂的第一浓度的第一掺杂外延层，并蚀刻第一掺杂外延层。 第二迭代进行的沉积和蚀刻工艺包括：在半导体衬底上沉积具有高于第一浓度的掺杂剂的第二浓度的第二掺杂外延层，并蚀刻第二掺杂外延层。 第一个浓度导致超过晶体管结构的第一净增长率，而第二浓度导致比晶体管结构高出测试结构的较低的第二净增长率，导致模式负载减小。