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1.发明授权Semiconductor device generating internal clock signal having higher frequency than that of input clock signal 有权产生具有比输入时钟信号频率高的内部时钟信号的半导体器件公开(公告)号：US09054713B2
公开(公告)日：2015-06-09
申请号：US13959119
申请日：2013-08-05
申请人： ELPIDA MEMORY, INC.
CPC分类号： H03L7/0802 , G11C7/222 , G11C11/4076 , G11C29/12015 , G11C29/14 , H03L7/0816 , H03L7/22
摘要： Disclosed herein is a device that includes: a plurality of delay circuits each including an input node, an output node, a first power node and a second power node, and a control circuit. The delay circuits are coupled in series with the input node of a leading delay circuit receiving a first clock signal and the output node of a last delay circuit producing a second clock signal. The control circuit coupled to receive the first and second clock signals to control an operating voltage supplied between the first and second power lines. The first power nodes of the delay circuits are connected in common to the first power line, and the second power nodes the delay circuits are connected in common to the second power line.
摘要翻译： 这里公开了一种装置，其包括：多个延迟电路，每个延迟电路包括输入节点，输出节点，第一功率节点和第二功率节点，以及控制电路。 延迟电路与接收第一时钟信号的前导延迟电路的输入节点和最后一个延迟电路的输出节点串联耦合，产生第二时钟信号。 控制电路被耦合以接收第一和第二时钟信号，以控制在第一和第二电力线之间提供的工作电压。 延迟电路的第一功率节点共同连接到第一电力线，并且第二电力节点延迟电路共同连接到第二电力线。
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公开(公告)号：US08760205B2
公开(公告)日：2014-06-24
申请号：US13794399
申请日：2013-03-11
申请人： Elpida Memory, Inc.
IPC分类号： H03K19/003
CPC分类号： H03K19/003 , H03K19/018521
摘要： A semiconductor device according to the present invention includes an input circuit that is connected between an input node and an output node and that changes a level of the output node corresponding to a signal supplied to the input node, wherein when a control signal represents a first mode, a speed at which input circuit changes the level of the output node from a first level to a second level is greater than the speed at which input circuit changes the level of the output node from the second level to the first level and when the control signal represents a second mode, the speed at which input circuit changes the level of the output node from the second level to the first level is greater than the speed at which the input circuit changes the level of the output node from the first level to the second level.
摘要翻译： 根据本发明的半导体器件包括输入电路，其连接在输入节点和输出节点之间，并且改变与提供给输入节点的信号相对应的输出节点的电平，其中当控制信号表示第一 输入电路将输出节点的电平从第一电平改变到第二电平的速度大于输入电路将输出节点的电平从第二电平改变到第一电平的速度，并且当 控制信号表示第二模式，输入电路将输出节点的电平从第二电平改变到第一电平的速度大于输入电路将输出节点的电平从第一电平改变为第一电平的速度 第二级。
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公开(公告)号：US20130207701A1
公开(公告)日：2013-08-15
申请号：US13761137
申请日：2013-02-06
发明人： Katsuhiro Kitagawa
IPC分类号： H03K5/06
CPC分类号： H03K5/06 , H03K5/1506 , H03K5/1565
摘要： Disclosed herein is a semiconductor device that includes: an input node; an output node; a plurality of variable delay circuits connected in series between the input node and the output node; a control circuit that commonly controls delay amounts of the variable delay circuits based on phases of a first clock signal supplied to the input node and a second clock signal output from the output node; and a mixer circuit that generates a third clock signal based on any one of input clock signals respectively input to the variable delay circuits and any one of output clock signals respectively output from the variable delay circuits.
摘要翻译： 本文公开了一种半导体器件，其包括：输入节点; 输出节点; 在输入节点和输出节点之间串联连接的多个可变延迟电路; 控制电路，其通常基于提供给输入节点的第一时钟信号的相位和从输出节点输出的第二时钟信号来控制可变延迟电路的延迟量; 以及混合电路，其基于分别输入到可变延迟电路的输入时钟信号和从可变延迟电路分别输出的任何一个输出时钟信号中的任何一个产生第三时钟信号。
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公开(公告)号：US08803576B2
公开(公告)日：2014-08-12
申请号：US13761137
申请日：2013-02-06
申请人： Elpida Memory, Inc.
发明人： Katsuhiro Kitagawa
CPC分类号： H03K5/06 , H03K5/1506 , H03K5/1565
摘要： Disclosed herein is a semiconductor device that includes: an input node; an output node; a plurality of variable delay circuits connected in series between the input node and the output node; a control circuit that commonly controls delay amounts of the variable delay circuits based on phases of a first clock signal supplied to the input node and a second clock signal output from the output node; and a mixer circuit that generates a third clock signal based on any one of input clock signals respectively input to the variable delay circuits and any one of output clock signals respectively output from the variable delay circuits.
摘要翻译： 本文公开了一种半导体器件，其包括：输入节点; 输出节点; 在输入节点和输出节点之间串联连接的多个可变延迟电路; 控制电路，其通常基于提供给输入节点的第一时钟信号的相位和从输出节点输出的第二时钟信号来控制可变延迟电路的延迟量; 以及混合电路，其基于分别输入到可变延迟电路的输入时钟信号和从可变延迟电路分别输出的任何一个输出时钟信号中的任何一个产生第三时钟信号。
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