公开(公告)号：US09934862B2

公开(公告)日：2018-04-03

申请号：US15424065

申请日：2017-02-03

Applicant: Empire Technology Development LLC

Inventor： Yanjun Ma ,  Edwin Kan

IPC: G11C16/06 ,  G11C16/26 ,  G11C7/08 ,  G11C7/10 ,  G11C11/54 ,  G11C11/56 ,  G11C13/00 ,  G11C16/24 ,  G11C16/32 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C7/08 ,  G11C7/1006 ,  G11C11/54 ,  G11C11/56 ,  G11C11/5621 ,  G11C11/5642 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0061 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/32 ,  G11C2211/5648

Abstract: Technologies are generally provided for methods and circuitry to rank a large number of cells in a timeframe of about one sense cycle. In some examples, an architecture may be implemented to rank memory cells such as volatile memories, non-volatile memories, and other types of data storage devices, where there may not be an equivalent to threshold voltage. In other examples, an arbitrary group of circuits, such as in neural networks where there may not be an equivalent control gate to set the timing resolution, may be ranked. Relative sense timing may be used to rank the cells having different current carrying abilities. A ramped gate voltage may be used to control the timing resolution and to reduce contention between close separate cells. Digital logic may be used to latch and/or record the rank information.

公开(公告)号：US09983991B2

公开(公告)日：2018-05-29

申请号：US15712475

申请日：2017-09-22

Applicant: Empire Technology Development LLC

Inventor： Edwin Kan

IPC: G06F12/00 ,  G11C7/10 ,  G11C16/10

CPC classification number: G06F12/00 ,  G11C7/1006 ,  G11C16/10

Abstract: Technologies are generally described to store data in single-level memory using rank modulation. In some examples, data to be encoded to single-level memory may be represented with a bit ranking for a group of bits. A program vector may then be determined from the bit ranking and partial program characteristics associated with the memory group(s). The memory group(s) may then be programmed according to the program vector. The encoded data may be subsequently retrieved by performing a series of partial programming operations on the memory group(s) to recover the bit ranking and derive the data represented.

公开(公告)号：US20180011785A1

公开(公告)日：2018-01-11

申请号：US15712475

申请日：2017-09-22

Applicant: Empire Technology Development LLC

Inventor： Edwin Kan

IPC: G06F12/00 ,  G11C16/10 ,  G11C7/10

CPC classification number: G06F12/00 ,  G11C7/1006 ,  G11C16/10

Abstract: Technologies are generally described to store data in single-level memory using rank modulation. In some examples, data to be encoded to single-level memory may be represented with a bit ranking for a group of bits. A program vector may then be determined from the bit ranking and partial program characteristics associated with the memory group(s). The memory group(s) may then be programmed according to the program vector. The encoded data may be subsequently retrieved by performing a series of partial programming operations on the memory group(s) to recover the bit ranking and derive the data represented.

公开(公告)号：US20170228185A1

公开(公告)日：2017-08-10

申请号：US15494109

申请日：2017-04-21

Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

Inventor： Edwin Kan

IPC: G06F3/06 ,  G11C7/00

CPC classification number: H04L9/3278 ,  G06F3/0623 ,  G06F3/0637 ,  G06F3/0638 ,  G06F3/0679 ,  G06F21/34 ,  G06F21/79 ,  G11C7/00 ,  G11C16/0408 ,  G11C16/10 ,  H04L9/0866

Abstract: Technologies are generally described for partial programming of memory having physically unclonable functions for secure data storage. In some examples, a sender that wishes to securely send data to a recipient using a physical memory may measure a program threshold average and a program threshold variation for bits in the memory and group the bits into different bins based on the measured average and variation. The sender may partially program the data to a set of bits selected from one or more of the bins by applying partial program pulses to the bits based on the program threshold average and the program threshold variation. The sender may then provide the partially-programmed memory to the recipient. The recipient may then partially program the received memory based on the program threshold average and the program threshold variation to recover the programmed data.

公开(公告)号：US20170148522A1

公开(公告)日：2017-05-25

申请号：US15424065

申请日：2017-02-03

Applicant: Empire Technology Development LLC

Inventor： Yanjun Ma ,  Edwin Kan

IPC: G11C16/26 ,  G11C13/00 ,  G11C16/32 ,  G11C16/24 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C7/08 ,  G11C7/1006 ,  G11C11/54 ,  G11C11/56 ,  G11C11/5621 ,  G11C11/5642 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0061 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/32 ,  G11C2211/5648

Abstract: Technologies are generally provided for methods and circuitry to rank a large number of cells in a timeframe of about one sense cycle. In some examples, an architecture may be implemented to rank memory cells such as volatile memories, non-volatile memories, and other types of data storage devices, where there may not be an equivalent to threshold voltage. In other examples, an arbitrary group of circuits, such as in neural networks where there may not be an equivalent control gate to set the timing resolution, may be ranked. Relative sense timing may be used to rank the cells having different current carrying abilities. A ramped gate voltage may be used to control the timing resolution and to reduce contention between close separate cells. Digital logic may be used to latch and/or record the rank information.

公开(公告)号：US20160077765A1

公开(公告)日：2016-03-17

申请号：US14488125

申请日：2014-09-16

Applicant: Empire Technology Development LLC

Inventor： Edwin Kan

IPC: G06F3/06

CPC classification number: G06F12/00 ,  G11C7/1006 ,  G11C16/10

Abstract: Technologies are generally described to store data in single-level memory using rank modulation. In some examples, data to be encoded to single-level memory may be represented with a bit ranking for a group of bits. A program vector may then be determined from the bit ranking and partial program characteristics associated with the memory group(s). The memory group(s) may then be programmed according to the program vector. The encoded data may be subsequently retrieved by performing a series of partial programming operations on the memory group(s) to recover the bit ranking and derive the data represented.

Abstract translation: 技术通常被描述为使用秩调制将数据存储在单级存储器中。 在一些示例中，要编码到单级存储器的数据可以用一组位的比特排列来表示。 然后可以根据与存储器组相关联的比特排序和部分程序特征来确定程序向量。 然后可以根据程序向量对存储器组进行编程。 可以随后通过对存储器组执行一系列部分编程操作来恢复编码数据，以恢复比特排序并导出表示的数据。

公开(公告)号：US09772935B2

公开(公告)日：2017-09-26

申请号：US14488125

申请日：2014-09-16

Applicant: Empire Technology Development LLC

Inventor： Edwin Kan

IPC: G06F12/00 ,  G11C7/10 ,  G11C16/10

CPC classification number: G06F12/00 ,  G11C7/1006 ,  G11C16/10

Abstract: Technologies are generally described to store data in single-level memory using rank modulation. In some examples, data to be encoded to single-level memory may be represented with a bit ranking for a group of bits. A program vector may then be determined from the bit ranking and partial program characteristics associated with the memory group(s). The memory group(s) may then be programmed according to the program vector. The encoded data may be subsequently retrieved by performing a series of partial programming operations on the memory group(s) to recover the bit ranking and derive the data represented.

公开(公告)号：US09646178B2

公开(公告)日：2017-05-09

申请号：US14515425

申请日：2014-10-15

Applicant: Empire Technology Development LLC

Inventor： Edwin Kan

IPC: H04L9/32 ,  G06F21/79 ,  G11C16/04 ,  G11C16/10 ,  H04L9/08 ,  G06F21/34

CPC classification number: G06F3/0623 ,  G06F3/0637 ,  G06F3/0638 ,  G06F3/0679 ,  G06F21/34 ,  G06F21/79 ,  G11C7/00 ,  G11C16/0408 ,  G11C16/10 ,  H04L9/0866 ,  H04L9/3278

Abstract: Technologies are generally described for partial programming of memory having physically unclonable functions for secure data storage. In some examples, a sender that wishes to securely send data to a recipient using a physical memory may measure a program threshold average and a program threshold variation for bits in the memory and group the bits into different bins based on the measured average and variation. The sender may partially program the data to a set of bits selected from one or more of the bins by applying partial program pulses to the bits based on the program threshold average and the program threshold variation. The sender may then provide the partially-programmed memory to the recipient. The recipient may then partially program the received memory based on the program threshold average and the program threshold variation to recover the programmed data.

公开(公告)号：US09589654B2

公开(公告)日：2017-03-07

申请号：US14647075

申请日：2014-04-15

Applicant: Empire Technology Development LLC

Inventor： Yanjun Ma ,  Edwin Kan

IPC: G11C16/04 ,  G11C16/26 ,  G11C7/08 ,  G11C7/10 ,  G11C11/54 ,  G11C11/56 ,  G11C13/00 ,  G11C16/24 ,  G11C16/32

CPC classification number: G11C16/26 ,  G11C7/08 ,  G11C7/1006 ,  G11C11/54 ,  G11C11/56 ,  G11C11/5621 ,  G11C11/5642 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0061 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/32 ,  G11C2211/5648

Abstract: Technologies are generally provided for methods and circuitry to rank a large number of cells in a timeframe of about one sense cycle. In some examples, an architecture may be implemented to rank memory cells such as volatile memories, non-volatile memories, and other types of data storage devices, where there may not be an equivalent to threshold voltage. In other examples, an arbitrary group of circuits, such as in neural networks where there may not be an equivalent control gate to set the timing resolution, may be ranked. Relative sense timing may be used to rank the cells having different current carrying abilities. A ramped gate voltage may be used to control the timing resolution and to reduce contention between close separate cells. Digital logic may be used to latch and/or record the rank information.

Abstract translation: 通常提供技术用于在大约一个感测周期的时间范围内对大量单元进行排序的方法和电路。 在一些示例中，可以实施一种架构来对诸如易失性存储器，非易失性存储器和其他类型的数据存储设备之类的存储器单元进行排序，其中可能没有等效于阈值电压。 在其他示例中，可以对任意组的电路进行排序，诸如在神经网络中，其中可能不存在用于设置定时分辨率的等效控制门。 可以使用相对感测定时对具有不同载流能力的单元进行排序。 可以使用斜坡栅极电压来控制定时分辨率并减少关闭分开的单元之间的竞争。 数字逻辑可用于锁存和/或记录秩信息。

公开(公告)号：US20160110130A1

公开(公告)日：2016-04-21

申请号：US14515425

申请日：2014-10-15

Applicant: Empire Technology Development LLC

Inventor： Edwin Kan

IPC: G06F3/06

CPC classification number: G06F3/0623 ,  G06F3/0637 ,  G06F3/0638 ,  G06F3/0679 ,  G06F21/34 ,  G06F21/79 ,  G11C7/00 ,  G11C16/0408 ,  G11C16/10 ,  H04L9/0866 ,  H04L9/3278

Abstract: Technologies are generally described for partial programming of memory having physically unclonable functions for secure data storage. In some examples, a sender that wishes to securely send data to a recipient using a physical memory may measure a program threshold average and a program threshold variation for bits in the memory and group the bits into different bins based on the measured average and variation. The sender may partially program the data to a set of bits selected from one or more of the bins by applying partial program pulses to the bits based on the program threshold average and the program threshold variation. The sender may then provide the partially-programmed memory to the recipient. The recipient may then partially program the received memory based on the program threshold average and the program threshold variation to recover the programmed data.

Abstract translation: 通常描述技术用于具有用于安全数据存储的物理上不可克隆功能的存储器的部分编程。 在一些示例中，希望使用物理存储器将数据安全地发送到接收方的发送器可以测量存储器中的位的程序阈值平均值和程序阈值变化，并且基于测量的平均值和变化将位组分组成不同的存储区。 基于程序阈值平均值和程序阈值变化，发送器可以通过将部分编程脉冲应用于位来将数据部分地编程为从一个或多个存储槽中选择的一组位。 然后，发送者可以向接收者提供部分编程的存储器。 接收者然后可以基于程序阈值平均值和程序阈值变化部分地对接收到的存储器进行编程以恢复编程数据。