公开(公告)号：US12290001B2

公开(公告)日：2025-04-29

申请号：US18526636

申请日：2023-12-01

Applicant: Everspin Technologies, Inc.

Inventor： Sanjeev Aggarwal ,  Sarin A. Deshpande ,  Kerry Joseph Nagel

IPC: H10N50/01 ,  H10B61/00

Abstract: A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes etching through a first portion of the magnetoresistive stack using a first etch process to form one or more sidewalls. At least a portion of the sidewalls includes redeposited material after the etching. The method also includes modifying at least a portion of the redeposited material on the sidewalls, and etching through a second portion of the magnetoresistive stack after the modifying step. The magnetoresistive stack may include a first magnetic region, an intermediate region disposed over the first magnetic region, and a second magnetic region disposed over the intermediate region.

公开(公告)号：US10658575B2

公开(公告)日：2020-05-19

申请号：US15808996

申请日：2017-11-10

Applicant: Everspin Technologies, Inc.

Inventor： Kerry Joseph Nagel

IPC: H01L43/12 ,  H01L23/544 ,  H01L43/02 ,  H01L43/08

Abstract: Techniques are presented for ensuring alignment marks are available for use and patterning magnetoresistive devices following the deposition of layers used to form the magnetoresistive devices. In some cases, the plurality of layers corresponding to the magnetoresistive devices are selectively etched in order to expose the underlying alignment marks, whereas in other embodiments, the deposition of the plurality of layers is controlled by deposition tool tabs that prevent the materials from obscuring the underlying alignment marks.

公开(公告)号：US10461250B2

公开(公告)日：2019-10-29

申请号：US16050749

申请日：2018-07-31

Applicant: Everspin Technologies, Inc.

Inventor： Sarin A. Deshpande ,  Kerry Joseph Nagel ,  Chaitanya Mudivarthi ,  Sanjeev Aggarwal

IPC: H01L43/12 ,  H01L43/08

Abstract: A method of manufacturing a magnetoresistive stack/structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer, (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.

公开(公告)号：US20160315253A1

公开(公告)日：2016-10-27

申请号：US15147682

申请日：2016-05-05

Applicant: Everspin Technologies, Inc.

Inventor： Sarin A. Deshpande ,  Sanjeev Aggarwal ,  Kerry Joseph Nagel ,  Chaitanya Mudivarthi ,  Nicholas Rizzo ,  Jason Allen Janesky

IPC: H01L43/12 ,  H01L43/08

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L43/08

Abstract: In forming a top electrode for a magnetoresistive device, photoresist used in patterning the electrode is stripped using a non-reactive stripping process. Such a non-reactive stripping process uses water vapor or some other non-oxidizing gas that also passivates exposed portions the magnetoresistive device. In such magnetoresistive devices, a non-reactive spacer layer is included that helps prevent diffusion between layers in the magnetoresistive device, where the non-reactive nature of the spacer layer prevents sidewall roughness that can interfere with accurate formation of the lower portions of the magnetoresistive device.

公开(公告)号：US20150357559A1

公开(公告)日：2015-12-10

申请号：US14297389

申请日：2014-06-05

Applicant: Everspin Technologies, Inc.

Inventor： Kerry Joseph Nagel ,  Sanjeev Aggarwal ,  Moazzem Hossain ,  Nicholas Rizzo

IPC: H01L43/08 ,  H01L43/12 ,  H01L45/00 ,  H01L43/02

CPC classification number: H01L27/222 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A layer of silicon nitride above the bottom electrode and on the sidewalls of the magnetoresistive stack serves as an insulator and an etch stop during manufacturing of a magnetoresistive device. Non-selective chemical mechanical polishing removes any silicon nitride overlying a top electrode for the device along with silicon dioxide used for encapsulation. Later etching operations corresponding to formation of a via to reach the top electrode use selective etching chemistries that remove silicon dioxide to access the top electrode, but do not remove silicon nitride. Thus, the silicon nitride acts as an etch stop, and, in the resulting device, provides an insulating layer that prevents unwanted short circuits between the via and the bottom electrode and between the via and the sidewalls of the magnetoresistive device stack.

Abstract translation: 在磁阻堆叠的底部电极和侧壁上方的氮化硅层用作磁阻器件的制造期间的绝缘体和蚀刻停止。 非选择性化学机械抛光除了用于器件的顶部电极以及用于封装的二氧化硅之外的任何氮化硅。 对应于形成通孔以到达顶部电极的后来的蚀刻操作使用去除二氧化硅以进入顶部电极但是不去除氮化硅的选择性蚀刻化学品。 因此，氮化硅用作蚀刻停止，并且在所得到的器件中提供了防止通孔和底部电极之间以及磁阻器件堆叠的通路和侧壁之间的不期望的短路的绝缘层。

公开(公告)号：US20150236249A1

公开(公告)日：2015-08-20

申请号：US14296189

申请日：2014-06-04

Applicant: Everspin Technologies, Inc.

Inventor： Sarin A. Deshpande ,  Kerry Joseph Nagel ,  Sanjeev Aggarwal ,  Chaitanya Mudivarthi

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/08

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L43/08

Abstract: In forming a top electrode for a magnetoresistive device, photoresist used in patterning the electrode is stripped using a non-reactive stripping process. Such a non-reactive stripping process uses water vapor or some other non-oxidizing gas that also passivates exposed portions the magnetoresistive device. In such magnetoresistive devices, a non-reactive spacer layer is included that helps prevent diffusion between layers in the magnetoresistive device, where the non-reactive nature of the spacer layer prevents sidewall roughness that can interfere with accurate formation of the lower portions of the magnetoresistive device.

Abstract translation: 在形成用于磁阻器件的顶部电极时，使用非反应性剥离工艺剥离用于图案化电极的光致抗蚀剂。 这种非反应性汽提方法使用水蒸汽或一些其它非氧化气体，其也钝化了磁阻装置的暴露部分。 在这种磁阻器件中，包括非反应性间隔层，其有助于防止磁阻器件中的层之间的扩散，其中间隔层的非反应性质防止可能干扰磁阻的下部的精确形成的侧壁粗糙度 设备。

公开(公告)号：US12075630B2

公开(公告)日：2024-08-27

申请号：US18045539

申请日：2022-10-11

Applicant: Everspin Technologies, Inc.

Inventor： Kerry Joseph Nagel ,  Sanjeev Aggarwal ,  Thomas Andre ,  Sarin A. Deshpande

IPC: H01L29/82 ,  G11C11/16 ,  H01L43/00 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80

CPC classification number: H10B61/00 ,  G11C11/161 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80

Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.

公开(公告)号：US12063865B2

公开(公告)日：2024-08-13

申请号：US16989155

申请日：2020-08-10

Applicant: Everspin Technologies, Inc.

Inventor： Sanjeev Aggarwal ,  Sarin A. Deshpande ,  Kerry Joseph Nagel

IPC: H10N50/01 ,  H10B61/00

CPC classification number: H10N50/01 ,  H10B61/00 ,  H10B61/22

Abstract: A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes etching through a first portion of the magnetoresistive stack using a first etch process to form one or more sidewalls. At least a portion of the sidewalls includes redeposited material after the etching. The method also includes modifying at least a portion of the redeposited material on the sidewalls, and etching through a second portion of the magnetoresistive stack after the modifying step. The magnetoresistive stack may include a first magnetic region, an intermediate region disposed over the first magnetic region, and a second magnetic region disposed over the intermediate region.

公开(公告)号：US11482570B2

公开(公告)日：2022-10-25

申请号：US17134865

申请日：2020-12-28

Applicant: Everspin Technologies, Inc.

Inventor： Kerry Joseph Nagel ,  Sanjeev Aggarwal ,  Thomas Andre ,  Sarin A. Deshpande

IPC: H01L29/82 ,  H01L43/00 ,  H01L27/22 ,  H01L43/08 ,  G11C11/16 ,  H01L43/12 ,  H01L43/02

Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.

公开(公告)号：US11031546B2

公开(公告)日：2021-06-08

申请号：US16194523

申请日：2018-11-19

Applicant: Everspin Technologies, Inc.

Inventor： Kerry Joseph Nagel ,  Kenneth H. Smith ,  Moazzem Hossain ,  Sanjeev Aggarwal

IPC: H01L21/3213 ,  H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  H01L21/768 ,  H01L21/285 ,  H01L43/02

Abstract: A method of manufacturing one or more interconnects to magnetoresistive structure comprising (i) depositing a first conductive material in a via; (2) etching the first conductive material wherein, after etching the first conductive material a portion of the first conductive material remains in the via, (3) partially filling the via by depositing a second conductive material in the via and directly on the first conductive material in the via; (4) depositing a first electrode material in the via and directly on the second conductive material in the via; (5) polishing a first surface of the first electrode material wherein, after polishing, the first electrode material is (i) on the second conductive material in the via and (ii) over the portion of the first conductive material remaining in the via; and (6) forming a magnetoresistive structure over the first electrode material.