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    Method of controlling program threshold voltage distribution of a dual cell memory device
    3.
    发明授权
    Method of controlling program threshold voltage distribution of a dual cell memory device 有权
    控制双电池存储器件的程序阈值电压分布的方法

    公开(公告)号：US06822909B1

    公开(公告)日：2004-11-23

    申请号：US10422090

    申请日：2003-04-24

    申请人： Darlene G. Hamilton ,  Edward Hsia ,  Mark W. Randolph ,  Edward F. Runnion ,  Kulachet Tanpairoj

    发明人： Darlene G. Hamilton ,  Edward Hsia ,  Mark W. Randolph ,  Edward F. Runnion ,  Kulachet Tanpairoj

    IPC分类号： G11C1134

    CPC分类号： G11C16/0475 ,  G11C11/5671 ,  G11C16/3454

    摘要： A method of programming a dual cell memory device having a first charge storing cell and a second charge storing cell. The method can include applying an initial program pulse to the memory device; comparing the threshold voltage of the memory device with a verify threshold voltage; and if the threshold voltage of the memory device is less than the verify threshold voltage, applying a second program pulse to the memory device during which at least one condition of the second program pulse is modified from the initial program pulse.

    摘要翻译： 一种编程具有第一电荷存储单元和第二电荷存储单元的双单元存储器件的方法。 该方法可以包括将初始编程脉冲施加到存储器件; 将存储器件的阈值电压与验证阈值电压进行比较; 并且如果所述存储器件的阈值电压小于所述验证​​阈值电压，则向所述存储器件施加第二编程脉冲，在所述存储器件期间，从所述初始编程脉冲修改所述第二编程脉冲的至少一个条件。

    Pre-charge method for reading a non-volatile memory cell
    4.
    发明授权
    Pre-charge method for reading a non-volatile memory cell 失效
    用于读取非易失性存储单元的预充电方法

    公开(公告)号：US06788583B2

    公开(公告)日：2004-09-07

    申请号：US10307749

    申请日：2002-12-02

    申请人： Yi He ,  Edward F. Runnion ,  Zhizheng Liu ,  Mark W. Randolph ,  Darlene G. Hamilton ,  Pauling Chen ,  Binh Le

    发明人： Yi He ,  Edward F. Runnion ,  Zhizheng Liu ,  Mark W. Randolph ,  Darlene G. Hamilton ,  Pauling Chen ,  Binh Le

    IPC分类号： G11C1606

    CPC分类号： G11C7/12 ,  G11C16/0475 ,  G11C16/24

    摘要： A method of detecting a charge stored on a charge storage region of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells comprises grounding a first bit line that forms a source junction with a channel region of the first memory cell. A high voltage is applied to a gate of the first memory cell and to a second bit line that is the next bit line to the right of the first bit line and separated from the first bit line only by the channel region. A third bit line, that is the next bit line to the right of the second bit line, is isolated such that its potential is effected only by its junctions with the a second channel region and a third channel region on opposing sides of the third bit line. A high voltage is applied to a pre-charge bit line that is to the right of the third bit line and current flow is detected at the second bit line to determine the programmed status of a source bit of the memory cell.

    摘要翻译： 一种检测存储在双位介质存储器单元阵列内的第一双位介质存储单元的电荷存储区域上的电荷的方法包括使与第一存储单元的沟道区形成源极结的第一位线接地。 高电压被施加到第一存储单元的栅极和第二位线，第二位线是第一位线右侧的下一个位线，并且仅与通道区域从第一位线分离。 位于第二位线右侧的下一个位线的第三位线是隔离的，使得其电位仅由其与第二通道区域的结和仅在第三位的相对侧上的第三通道区域 线。 将高电压施加到位于第三位线右侧的预充电位线，并且在第二位线处检测电流以确定存储器单元的源位的编程状态。

    Method of programming a dual cell memory device
    5.
    发明授权
    Method of programming a dual cell memory device 失效
    编程双单元存储器件的方法

    公开(公告)号：US06775187B1

    公开(公告)日：2004-08-10

    申请号：US10422489

    申请日：2003-04-24

    申请人： Darlene G. Hamilton ,  Edward F. Runnion ,  Edward Hsia ,  Kulachet Tanpairoj

    发明人： Darlene G. Hamilton ,  Edward F. Runnion ,  Edward Hsia ,  Kulachet Tanpairoj

    IPC分类号： G11C1604

    CPC分类号： G11C16/10 ,  G11C16/0475

    摘要： A method of programming a dual cell memory device having a first charge storing cell and second charge storing cell. The first charge storing cell can be pre-read to determine if the first charge storing cell stores an amount of charge to increase a threshold voltage of the memory device over a specified threshold voltage. If not, the second charge storing cell can be programmed with a standard program pulse. If so, the second charge storing cell can be programed with a modified program pulse.

    摘要翻译： 一种编程具有第一电荷存储单元和第二电荷存储单元的双单元存储器件的方法。 可以预先读取第一电荷存储单元，以确定第一电荷存储单元是否存储一定量的电荷以增加存储器件的阈值电压超过指定的阈值电压。 如果不是，则可以用标准编程脉冲编程第二电荷存储单元。 如果是这样，则可以用修改的编程脉冲对第二电荷存储单元进行编程。

    Methods and systems for reducing the threshold voltage distribution following a memory cell erase
    7.
    发明授权
    Methods and systems for reducing the threshold voltage distribution following a memory cell erase 有权
    减少存储单元擦除后阈值电压分布的方法和系统

    公开(公告)号：US07170796B1

    公开(公告)日：2007-01-30

    申请号：US11193391

    申请日：2005-08-01

    申请人： Yi He ,  Gwyn Jones ,  Edward F. Runnion ,  Mark Randolph

    发明人： Yi He ,  Gwyn Jones ,  Edward F. Runnion ,  Mark Randolph

    IPC分类号： G11C11/34

    CPC分类号： G11C16/14 ,  G11C16/3468 ,  G11C16/3472 ,  G11C16/3477

    摘要： A method is provided for erasing a memory device including a number of memory cells, the memory cells including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes erasing a group of memory cells to lower a maximum threshold voltage of the group of memory cells below a first predetermined level. The group of memory cells is soft-programmed to raise a minimum threshold voltage of the group of memory cells above a second predetermined level. The group of memory cells is erased, following soft-programming, resulting in a reduced threshold voltage distribution associated with the group of memory cells.

    摘要翻译： 提供了一种用于擦除包括多个存储单元的存储器件的方法，所述存储器单元包括衬底，控制栅极，电荷存储元件，源极区域和漏极区域。 该方法包括擦除一组存储器单元以将存储器单元组的最大阈值电压降低到低于第一预定水平。 存储器单元组被软编程以将存储器单元组的最小阈值电压提高到高于第二预定水平。 在软编程之后，存储单元组被擦除，导致与该组存储器单元相关联的阈值电压分布降低。