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    Method of protecting a memory array from charge damage during fabrication
    2.
    发明授权
    Method of protecting a memory array from charge damage during fabrication 有权
    在制造期间保护存储器阵列免受电荷损伤的方法

    公开(公告)号：US06897110B1

    公开(公告)日：2005-05-24

    申请号：US10305750

    申请日：2002-11-26

    申请人： Yi He ,  Wei Zheng ,  Zhizheng Liu ,  Mark W. Randolph ,  Darlene G. Hamilton ,  Ken Tanpairoj

    发明人： Yi He ,  Wei Zheng ,  Zhizheng Liu ,  Mark W. Randolph ,  Darlene G. Hamilton ,  Ken Tanpairoj

    IPC分类号： H01L21/336 ,  H01L21/4763 ,  H01L23/525

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of fabricating a memory array, while protecting it from charge damage. Bitlines that may have source/drain regions of memory cells are formed in a substrate. Wordlines are formed above the bitlines and may have gate regions. Next, a first metal region that is coupled to one of the bitlines is formed above the bitlines. A second metal region that is not electrically coupled to the first metal region is formed. Then, the first metal region is electrically coupled to the second metal region. Charge damage is reduced by keeping the antenna ratio between the first metal region and the bitline low. For further protection, a diode or fuse may also be formed between the substrate and the portion of the metal region that is coupled to the bitline. Also, fuse may be formed between a bitline and a wordline to protect the wordline.

    摘要翻译： 一种制造存储器阵列的方法，同时保护其免受电荷损坏。 可以在衬底中形成可能具有存储器单元的源极/漏极区的位线。 字线形成在位线之上，并且可以具有栅极区域。 接下来，在位线之上形成耦合到位线之一的第一金属区域。 形成不与第一金属区电耦合的第二金属区域。 然后，第一金属区域电耦合到第二金属区域。 通过保持第一金属区域和位线之间的天线比率降低来减少电荷损坏。 为了进一步的保护，还可以在衬底和耦合到位线的金属区域的部分之间形成二极管或保险丝。 此外，可以在位线和字线之间形成保险丝，以保护字线。

    Back-to-back NPN/PNP protection diodes
    3.
    发明授权
    Back-to-back NPN/PNP protection diodes 有权
    背对背NPN / PNP保护二极管

    公开(公告)号：US07573103B1

    公开(公告)日：2009-08-11

    申请号：US11855704

    申请日：2007-09-14

    申请人： Yi He ,  Zhizheng Liu ,  Meng Ding ,  Wei Zheng

    发明人： Yi He ,  Zhizheng Liu ,  Meng Ding ,  Wei Zheng

    IPC分类号： H01L27/06

    CPC分类号： H01L27/0266 ,  H01L27/0255

    摘要： A device includes a memory device and an NPN or PNP diode coupled to a word-line of the memory device. The NPN diode includes a p-type substrate connected to ground, a well of n-type material formed in the p-type substrate in direct physical contact with the p-type substrate and electrically connected to the p-type substrate via a first metal line, a well of p-type material formed in the first well of n-type material, a first n-type region formed in the well of p-type material in direct physical contact with the well of p-type material and connected to the word line of the memory device, and a first p-type region formed in the well of n-type material in direct physical contact with the well of n-type material and electrically connected to the well of p-type material via a second metal line. The PNP diode includes a n-type substrate connected to ground, a well of p-type material formed in the n-type substrate in direct physical contact with the n-type substrate and electrically connected to the n-type substrate via a first metal line, a well of n-type material formed in the first well of p-type material, a first p-type region formed in the well of n-type material in direct physical contact with the well of n-type material and connected to the word line of the memory device, and a first n-type region formed in the well of p-type material in direct physical contact with the well of p-type material and electrically connected to the well of n-type material via a second metal line.

    摘要翻译： 一种设备包括存储器件和耦合到存储器件的字线的NPN或PNP二极管。 NPN二极管包括连接到地的p型衬底，在p型衬底中形成的与p型衬底直接物理接触的n型材料的阱，并通过第一金属电连接到p型衬底 线，在n型材料的第一阱中形成的p型材料的阱，形成在p型材料的阱中的第一n型区，与p型材料的阱直接物理接触并连接到 存储器件的字线和形成在n型材料的阱中的与n型材料的阱直接物理接触并且经由第二p型材料电连接到p型材料的阱的第一p型区域 金属线。 PNP二极管包括连接到地的n型衬底，形成在n型衬底中的p型材料的阱与n型衬底直接物理接触并且经由第一金属电连接到n型衬底 线，在p型材料的第一阱中形成的n型材料的阱，形成在n型材料的阱中的与n型材料的阱直接物理接触的第一p型区，并连接到 存储器件的字线和形成在p型材料的阱中的第一n型区域，其与p型材料的阱直接物理接触并且经由第二类型的n型材料电连接到n型材料的阱 金属线。

    Back-to-back NPN/PNP protection diodes
    5.
    发明授权
    Back-to-back NPN/PNP protection diodes 有权
    背对背NPN / PNP保护二极管

    公开(公告)号：US07285827B1

    公开(公告)日：2007-10-23

    申请号：US11194449

    申请日：2005-08-02

    申请人： Yi He ,  Zhizheng Liu ,  Meng Ding ,  Wei Zheng

    发明人： Yi He ,  Zhizheng Liu ,  Meng Ding ,  Wei Zheng

    IPC分类号： H01L23/62

    CPC分类号： H01L27/0266 ,  H01L27/0255

    摘要： A device includes a memory device and an NPN or PNP diode coupled to a word-line of the memory device. The NPN or PNP diode reduces device damage and performance impairment that may result from device charging by drawing charges away from the memory device.

    摘要翻译： 一种设备包括存储器件和耦合到存储器件的字线的NPN或PNP二极管。 NPN或PNP二极管通过从存储器件中抽取电荷来减少设备充电所造成的器件损坏和性能损害。

    SELECTIVE APPLICATION OF WORD LINE BIAS TO MINIMIZE FRINGE EFFECTS IN ELECTROMAGNETIC FIELDS DURING ERASE OF NONVOLATILE MEMORY
    7.
    发明申请
    SELECTIVE APPLICATION OF WORD LINE BIAS TO MINIMIZE FRINGE EFFECTS IN ELECTROMAGNETIC FIELDS DURING ERASE OF NONVOLATILE MEMORY 有权
    选择性应用字线偏移以最小化非易失性存储器中的电磁场中的影响

    公开(公告)号：US20100208527A1

    公开(公告)日：2010-08-19

    申请号：US12773232

    申请日：2010-05-04

    申请人： Gulzar Ahmed Kathawala ,  Wei Zheng ,  Zhizheng Liu ,  Sung-Yong Chung ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Sheung-Hee Park ,  Gabrielle Wing Han Leung

    发明人： Gulzar Ahmed Kathawala ,  Wei Zheng ,  Zhizheng Liu ,  Sung-Yong Chung ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Sheung-Hee Park ,  Gabrielle Wing Han Leung

    IPC分类号： G11C16/04

    CPC分类号： G11C16/3418

    摘要： A memory device comprising an optimization component that facilitates erasing memory cells in a substantially homogeneous electromagnetic field and methods that facilitate erasing memory cells in a substantially homogeneous electromagnetic field are presented. The optimization component facilitates selecting a subset of memory cells to be erased at the same time, such that a memory cell in the subset of memory cells has two neighbor memory cells adjacent thereto that are in the subset of memory, or one neighbor memory cell adjacent thereto when the memory cell is an end-row memory cell. The optimization component facilitates performing a Fowler-Nordheim channel erase to erase the subset of memory cells, and a predetermined voltage potential associated with an erase command is applied to each cell of the subset of memory cells to facilitate reducing fringing effect associated with the electromagnetic fields applied to the cells during the erase.

    摘要翻译： 提供了一种存储器件，其包括便于擦除基本上均匀的电磁场中的存储器单元的优化部件，以及便于在基本均匀的电磁场中擦除存储器单元的方法。 优化组件有助于同时选择要擦除的存储器单元的子集，使得存储器单元子集中的存储单元具有与存储单元相邻的两个相邻存储器单元，其位于存储器的子集中，或者相邻的一个相邻存储器单元 当存储器单元是端行存储单元时。 优化组件有助于执行Fowler-Nordheim信道擦除来擦除存储器单元的子集，并且与擦除命令相关联的预定电压电位被施加到存储器单元子集的每个单元，以便于减少与电磁场相关联的边缘效应 在擦除期间应用于细胞。

    Programming in memory devices using source bitline voltage bias
    8.
    发明授权
    Programming in memory devices using source bitline voltage bias 有权
    使用源位线电压偏置对存储器件进行编程

    公开(公告)号：US07746698B2

    公开(公告)日：2010-06-29

    申请号：US11956032

    申请日：2007-12-13

    申请人： Zhizheng Liu ,  An Chen ,  Wei Zheng ,  Kuo-Tung Chang ,  Sung-Yong Chung ,  Gulzar Ahmed Kathawala ,  Ashot Melik-Martirosian

    发明人： Zhizheng Liu ,  An Chen ,  Wei Zheng ,  Kuo-Tung Chang ,  Sung-Yong Chung ,  Gulzar Ahmed Kathawala ,  Ashot Melik-Martirosian

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0491 ,  G11C16/12

    摘要： Systems and methods that facilitate improved programming memory cells in a nonvolatile memory (e.g., flash memory) are presented. An optimized voltage component can facilitate supplying respective voltages to a source, drain, and gate associated with a memory cell during operations, such as programming operations. The optimized voltage component can facilitate supplying a predetermined source bitline voltage to a memory cell during programming of the cell to facilitate reducing leakage currents associated with the bitlines, which can improve programming of the memory cell, and to facilitate reducing the programming current, which can result in power efficient programming and improved programming speed.

    摘要翻译： 提出了有助于改进非易失性存储器（例如闪速存储器）中的编程存储器单元的系统和方法。 优化的电压分量可以有助于在诸如编程操作的操作期间向与存储器单元相关联的源极，漏极和栅极提供相应的电压。 优化的电压分量可以有助于在单元的编程期间向存储器单元提供预定的源位线电压，以便于减少与位线相关联的泄漏电流，这可以改善存储器单元的编程，并且有助于减少编程电流， 导致功率有效的编程和改进的编程速度。

    Selective Application Of Word Line Bias To Minimize Fringe Effects In Electromagnetic Fields During Erase Of Nonvolatile Memory
    9.
    发明申请
    Selective Application Of Word Line Bias To Minimize Fringe Effects In Electromagnetic Fields During Erase Of Nonvolatile Memory 有权
    在非易失性存储器擦除期间，字线偏置的选择性应用以最小化电磁场中的边缘效应

    公开(公告)号：US20090147589A1

    公开(公告)日：2009-06-11

    申请号：US11953689

    申请日：2007-12-10

    申请人： Gulzar Ahmed Kathawala ,  Wei Zheng ,  Zhizheng Liu ,  Sung-Yong Chung ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Sheung-Hee Park ,  Gabrielle Wing Han Leung

    发明人： Gulzar Ahmed Kathawala ,  Wei Zheng ,  Zhizheng Liu ,  Sung-Yong Chung ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Sheung-Hee Park ,  Gabrielle Wing Han Leung

    IPC分类号： G11C16/18

    CPC分类号： G11C16/3418

    摘要： A memory device comprising an optimization component that facilitates erasing memory cells in a substantially homogeneous electromagnetic field and methods that facilitate erasing memory cells in a substantially homogeneous electromagnetic field are presented. The optimization component facilitates selecting a subset of memory cells to be erased at the same time, such that a memory cell in the subset of memory cells has two neighbor memory cells adjacent thereto that are in the subset of memory, or one neighbor memory cell adjacent thereto when the memory cell is an end-row memory cell. The optimization component facilitates performing a Fowler-Nordheim channel erase to erase the subset of memory cells, and a predetermined voltage potential associated with an erase command is applied to each cell of the subset of memory cells to facilitate reducing fringing effect associated with the electromagnetic fields applied to the cells during the erase.

    摘要翻译： 提供了一种存储器件，其包括便于擦除基本上均匀的电磁场中的存储器单元的优化部件，以及便于在基本均匀的电磁场中擦除存储器单元的方法。 优化组件有助于同时选择要擦除的存储器单元的子集，使得存储器单元子集中的存储单元具有与存储单元相邻的两个相邻存储器单元，其位于存储器的子集中，或者相邻的一个相邻存储器单元 当存储器单元是端行存储单元时。 优化组件有助于执行Fowler-Nordheim信道擦除来擦除存储器单元的子集，并且与擦除命令相关联的预定电压电位被施加到存储器单元子集的每个单元，以便于减少与电磁场相关联的边缘效应 在擦除期间应用于细胞。

    Selective application of word line bias to minimize fringe effects in electromagnetic fields during erase of nonvolatile memory
    10.
    发明授权
    Selective application of word line bias to minimize fringe effects in electromagnetic fields during erase of nonvolatile memory 有权
    选择性地应用字线偏置，以最大限度地减少非易失性存储器擦除期间电磁场中的边缘效应

    公开(公告)号：US07746705B2

    公开(公告)日：2010-06-29

    申请号：US11953689

    申请日：2007-12-10

    申请人： Gulzar Ahmed Kathawala ,  Wei Zheng ,  Zhizheng Liu ,  Sung-Yong Chung ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Sheung-Hee Park ,  Gabrielle Wing Han Leung

    发明人： Gulzar Ahmed Kathawala ,  Wei Zheng ,  Zhizheng Liu ,  Sung-Yong Chung ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Sheung-Hee Park ,  Gabrielle Wing Han Leung

    IPC分类号： G11C16/04

    CPC分类号： G11C16/3418

    摘要： A memory device comprising an optimization component that facilitates erasing memory cells in a substantially homogeneous electromagnetic field and methods that facilitate erasing memory cells in a substantially homogeneous electromagnetic field are presented. The optimization component facilitates selecting a subset of memory cells to be erased at the same time, such that a memory cell in the subset of memory cells has two neighbor memory cells adjacent thereto that are in the subset of memory, or one neighbor memory cell adjacent thereto when the memory cell is an end-row memory cell. The optimization component facilitates performing a Fowler-Nordheim channel erase to erase the subset of memory cells, and a predetermined voltage potential associated with an erase command is applied to each cell of the subset of memory cells to facilitate reducing fringing effect associated with the electromagnetic fields applied to the cells during the erase.

    摘要翻译： 提供了一种存储器件，其包括便于擦除基本上均匀的电磁场中的存储器单元的优化部件，以及便于在基本均匀的电磁场中擦除存储器单元的方法。 优化组件有助于同时选择要擦除的存储器单元的子集，使得存储器单元子集中的存储单元具有与存储单元相邻的两个相邻存储器单元，其位于存储器的子集中，或者相邻的一个相邻存储器单元 当存储器单元是端行存储单元时。 优化组件有助于执行Fowler-Nordheim信道擦除来擦除存储器单元的子集，并且与擦除命令相关联的预定电压电位被施加到存储器单元子集的每个单元，以便于减少与电磁场相关联的边缘效应 在擦除期间应用于细胞。