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    Method of programming a dual cell memory device
    1.
    发明授权
    Method of programming a dual cell memory device 失效
    编程双单元存储器件的方法

    公开(公告)号：US06775187B1

    公开(公告)日：2004-08-10

    申请号：US10422489

    申请日：2003-04-24

    申请人： Darlene G. Hamilton ,  Edward F. Runnion ,  Edward Hsia ,  Kulachet Tanpairoj

    发明人： Darlene G. Hamilton ,  Edward F. Runnion ,  Edward Hsia ,  Kulachet Tanpairoj

    IPC分类号： G11C1604

    CPC分类号： G11C16/10 ,  G11C16/0475

    摘要： A method of programming a dual cell memory device having a first charge storing cell and second charge storing cell. The first charge storing cell can be pre-read to determine if the first charge storing cell stores an amount of charge to increase a threshold voltage of the memory device over a specified threshold voltage. If not, the second charge storing cell can be programmed with a standard program pulse. If so, the second charge storing cell can be programed with a modified program pulse.

    摘要翻译： 一种编程具有第一电荷存储单元和第二电荷存储单元的双单元存储器件的方法。 可以预先读取第一电荷存储单元，以确定第一电荷存储单元是否存储一定量的电荷以增加存储器件的阈值电压超过指定的阈值电压。 如果不是，则可以用标准编程脉冲编程第二电荷存储单元。 如果是这样，则可以用修改的编程脉冲对第二电荷存储单元进行编程。

    Method of controlling program threshold voltage distribution of a dual cell memory device
    2.
    发明授权
    Method of controlling program threshold voltage distribution of a dual cell memory device 有权
    控制双电池存储器件的程序阈值电压分布的方法

    公开(公告)号：US06822909B1

    公开(公告)日：2004-11-23

    申请号：US10422090

    申请日：2003-04-24

    申请人： Darlene G. Hamilton ,  Edward Hsia ,  Mark W. Randolph ,  Edward F. Runnion ,  Kulachet Tanpairoj

    发明人： Darlene G. Hamilton ,  Edward Hsia ,  Mark W. Randolph ,  Edward F. Runnion ,  Kulachet Tanpairoj

    IPC分类号： G11C1134

    CPC分类号： G11C16/0475 ,  G11C11/5671 ,  G11C16/3454

    摘要： A method of programming a dual cell memory device having a first charge storing cell and a second charge storing cell. The method can include applying an initial program pulse to the memory device; comparing the threshold voltage of the memory device with a verify threshold voltage; and if the threshold voltage of the memory device is less than the verify threshold voltage, applying a second program pulse to the memory device during which at least one condition of the second program pulse is modified from the initial program pulse.

    摘要翻译： 一种编程具有第一电荷存储单元和第二电荷存储单元的双单元存储器件的方法。 该方法可以包括将初始编程脉冲施加到存储器件; 将存储器件的阈值电压与验证阈值电压进行比较; 并且如果所述存储器件的阈值电压小于所述验证​​阈值电压，则向所述存储器件施加第二编程脉冲，在所述存储器件期间，从所述初始编程脉冲修改所述第二编程脉冲的至少一个条件。

    Method of determining charge loss activation energy of a memory array
    5.
    发明授权
    Method of determining charge loss activation energy of a memory array 失效
    确定存储器阵列的电荷损耗激活能的方法

    公开(公告)号：US06813752B1

    公开(公告)日：2004-11-02

    申请号：US10306667

    申请日：2002-11-26

    申请人： Edward Hsia ,  Darlene G. Hamilton ,  Wei Zheng ,  Mark W. Randolph ,  Kulachet Tanpairoj

    发明人： Edward Hsia ,  Darlene G. Hamilton ,  Wei Zheng ,  Mark W. Randolph ,  Kulachet Tanpairoj

    IPC分类号： G06F1750

    CPC分类号： G11C29/50 ,  G11C16/04

    摘要： A method of determining charge loss activation for a memory array. Memory arrays are programmed with a pattern for testing charge loss. Then, respective bake times are calculated for the memory arrays to experience a given amount of charge loss at their respective bake temperatures. Then, charge loss activation energy is calculated, based on the respective bake times. In one version, the memory arrays are cycled by repeatedly erasing and reprogramming them before baking. In another embodiment, various regions of the memory arrays are programmed to a plurality of distinct delta threshold voltages before baking.

    摘要翻译： 确定存储器阵列的电荷损失激活的方法。 存储器阵列被编程用于测试电荷损失的模式。 然后，对于存储器阵列计算各自的烘烤时间，以在其各自的烘烤温度下经历给定量的电荷损失。 然后，基于相应的烘烤时间计算电荷损失激活能。 在一个版本中，通过在烘烤之前重复擦除和重新编程它们来循环存储器阵列。 在另一个实施例中，存储器阵列的各个区域在烘烤之前被编程为多个不同的增量阈值电压。

    Method of dual cell memory device operation for improved end-of-life read margin
    6.
    发明授权
    Method of dual cell memory device operation for improved end-of-life read margin 有权
    双电池存储器件操作方法，用于改善寿命终止读取余量

    公开(公告)号：US06778442B1

    公开(公告)日：2004-08-17

    申请号：US10422092

    申请日：2003-04-24

    申请人： Darlene G. Hamilton ,  Edward Hsia ,  Kulachet Tanpairoj ,  Alykhan Madhani ,  Mimi Lee

    发明人： Darlene G. Hamilton ,  Edward Hsia ,  Kulachet Tanpairoj ,  Alykhan Madhani ,  Mimi Lee

    IPC分类号： G11C1134

    CPC分类号： G11C11/5671 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3454

    摘要： A method of programming a dual cell memory device having a first charge storing cell and a second charge storing cell. According to one aspect of the method, the method can include over-erasing the first and second charge storing cells to shift an erase state threshold voltage of the memory device to be lower than a natural state threshold voltage. According to another aspect of the method, the method can include programming the first and second charge storing cells to the same data state and verifying that the second programmed charge storing cell stores charge corresponding to the data state. If the verification fails, both charge storing cells can be re-pulsed.

    摘要翻译： 一种编程具有第一电荷存储单元和第二电荷存储单元的双单元存储器件的方法。 根据该方法的一个方面，该方法可以包括过度擦除第一和第二电荷存储单元，以使存储器件的擦除状态阈值电压低于自然状态阈值电压。 根据该方法的另一方面，该方法可以包括将第一和第二电荷存储单元编程为相同的数据状态，并验证第二编程电荷存储单元存储对应于数据状态的电荷。 如果验证失败，则电荷存储单元可以被重新脉冲。

    Erase method for a dual bit memory cell
    9.
    发明授权
    Erase method for a dual bit memory cell 有权
    双位存储单元的擦除方法

    公开(公告)号：US06901010B1

    公开(公告)日：2005-05-31

    申请号：US10119366

    申请日：2002-04-08

    申请人： Darlene G. Hamilton ,  Eric M. Ajimine ,  Binh Le ,  Edward Hsia ,  Ken Tanpairoj

    发明人： Darlene G. Hamilton ,  Eric M. Ajimine ,  Binh Le ,  Edward Hsia ,  Ken Tanpairoj

    IPC分类号： G11C16/02 ,  G11C16/04 ,  G11C7/00

    CPC分类号： G11C16/107 ,  G11C16/0475 ,  G11C16/3409 ,  G11C16/3445 ,  G11C2216/18

    摘要： An erase methodology of flash memory cells in a multi-bit memory array with bits disposed in normal and complimentary locations. An erase verify of bits in the normal locations is performed and if a bit in the normal location fails and if the maximum erase pulse count has not been reached, erase pulses are applied to both the normal bit and the complimentary bit. An erase verify of bits in the complimentary locations is performed and if a bit in the complimentary location fails and if the maximum erase pulse count has not been reached, erase pulses are applied to both the complimentary and the normal bit locations. If the bits pass the erase verify, the bits are subjected to a soft programming verify. If the bits are overerased and if the soft programming pulse count has not been reached a soft programming pulse is applied to the overerased bit.

    摘要翻译： 位于正常和互补位置的位的多位存储器阵列中的闪存单元的擦除方法。 执行正常位置中的位的擦除验证，并且如果正常位置中的位失败，并且如果还没有达到最大擦除脉冲计数，则将擦除脉冲施加到正常位和补充位。 执行补充位置中的位的擦除验证，并且如果补充位中的位失败，并且如果还没有达到最大擦除脉冲计数，则擦除脉冲将被施加到互补位和正常位位置。 如果这些位通过擦除验证，则这些位经过软编程验证。 如果这些位过高，并且如果没有达到软编程脉冲计数，则软编程脉冲将被施加到过高位。

    Method for reading a non-volatile memory cell adjacent to an inactive region of a non-volatile memory cell array
    10.
    发明授权
    Method for reading a non-volatile memory cell adjacent to an inactive region of a non-volatile memory cell array 有权
    用于读取与非易失性存储单元阵列的非活动区域相邻的非易失性存储单元的方法

    公开(公告)号：US06771545B1

    公开(公告)日：2004-08-03

    申请号：US10353558

    申请日：2003-01-29

    申请人： Edward Hsia ,  Eric Ajimine ,  Darlene G. Hamilton ,  Pauling Chen ,  Ming-Huei Shieh ,  Mark W. Randolph ,  Edward Runnion ,  Yi He

    发明人： Edward Hsia ,  Eric Ajimine ,  Darlene G. Hamilton ,  Pauling Chen ,  Ming-Huei Shieh ,  Mark W. Randolph ,  Edward Runnion ,  Yi He

    IPC分类号： G11C1604

    CPC分类号： G11C29/82 ,  G11C16/0491 ,  G11C16/3404

    摘要： An array of non-volatile memory cells includes active columns of cells wherein a data pattern may be stored adjacent to damaged or inactive columns wherein data is not stored. A method of storing a data pattern and reproducing the data pattern within such an array comprises storing a charge within a selected plurality of the memory cells within the active column. The selected plurality of memory cells represents a portion of the data pattern. An inactive memory cell programming pattern is identified. The inactive memory cell programming pattern identifies all, or a selected plurality, of the memory cells in the inactive column in which a charge is to be stored for the purpose of periodically storing a charge in the memory cells first inactive column to prevent over erasure, during bulk erase, and leakage from the inactive cells to adjacent active cells. A charge is stored on the selected plurality of the memory cells in the first inactive column. The data pattern is reproduced reading each memory cell within the first active column.

    摘要翻译： 非易失性存储器单元的阵列包括有效的单元格列，其中数据模式可以存储在与不存储数据的损坏或非活动列相邻的位置。 存储数据模式并在其中再现数据模式的方法包括将电荷存储在活动列内的所选择的多个存储单元内。 所选择的多个存储单元表示数据模式的一部分。 识别非活动存储器单元编程模式。 非活动存储器单元编程模式识别要在其中存储电荷的所述非活动列中的所有或选定的多个存储单元，以便在存储单元的第一非活动列中周期性地存储电荷以防止过度擦除， 在批量擦除期间以及从非活性电池泄漏到相邻的活性电池。 在第一非活动列中的所选择的多个存储器单元上存储电荷。 读取在第一活动列内的每个存储单元的数据模式。