公开(公告)号：US5384272A

公开(公告)日：1995-01-24

申请号：US266744

申请日：1994-06-28

申请人： Effiong E. Ibok ,  Bradley T. Moore

发明人： Effiong E. Ibok ,  Bradley T. Moore

IPC分类号： H01L21/336 ,  H01L27/115 ,  H01L21/266

CPC分类号： H01L29/66825 ,  H01L27/115

摘要： The invention provides a method for manufacturing a non-volatile, virtual ground memory element. The method includes the steps of depositing a first polysilicon layer on gate oxide on a silicon substrate, depositing or growing a first oxide layer, depositing a barrier nitride layer and patterning the first polysilicon layer, the first oxide layer and the barrier nitride layer to form a floating gate. The method further includes the steps of doping a region of the silicon substrate adjacent the floating gate to form a bit line region and oxidizing the bit line region in a wet ambient. The method further includes the use of a spacer nitride or spacer oxide/nitride layer to protect the edge of the floating gate during oxidation and to reduce dopant diffusion under the gate. The method further includes the steps of stripping the barrier nitride layer, depositing a second polysilicon layer and patterning the second polysilicon layer to form a control gate.

摘要翻译： 本发明提供一种用于制造非易失性虚拟地面存储元件的方法。 该方法包括以下步骤：在硅衬底上的栅极氧化物上沉积第一多晶硅层，沉积或生长第一氧化物层，沉积势垒氮化物层和图案化第一多晶硅层，第一氧化物层和势垒氮化物层以形成 一个浮动门。 该方法还包括以下步骤：在与浮置栅极相邻的硅衬底的区域中掺杂以形成位线区域并在湿环境中氧化位线区域。 该方法还包括使用间隔氮化物或间隔氧化物/氮化物层来在氧化期间保护浮置栅极的边缘并且减少栅极下方的掺杂剂扩散。 该方法还包括剥离势垒氮化物层，沉积第二多晶硅层和图案化第二多晶硅层以形成控制栅极的步骤。

公开(公告)号：US06235456B1

公开(公告)日：2001-05-22

申请号：US09208350

申请日：1998-12-09

申请人： Effiong E. Ibok

发明人： Effiong E. Ibok

IPC分类号： G03C1815

CPC分类号： G03F7/091

摘要： This invention provides methods for manufacturing anti-reflective barrier and/or polish-stop layers on semiconductors. The anti-reflective barrier and/or polish-stop layers permit more accurate photolithography during the manufacture of semiconductor devices. The barrier and/or polish-stop layers can comprise nitride and/or oxynitride films having non-stoichiometric ratios of silicon to nitrogen atoms within the film structure. The non-stoichiometry permits the films to be semi-transparent, decreasing transmission of electromagnetic radiation through the layers, thereby decreasing the reflection of the electromagnetic radiation back through the photoresist layers. By decreasing the reflection of the electromagnetic radiation through the photoresist materials, the effects of diffraction by mask edges and standing wave interference can be reduced, thereby permitting the more accurate, reproducible inscription of patterns onto semiconductor devices. Further, by simple modifications of existing methods for depositing barrier and/or polish-stop layers, the production of the anti-reflective layers of this invention can be incorporated easily into the overall manufacturing process, thereby minimizing the additional costs and time require for semiconductor manufacture. The invention also includes semiconductor devices made using the anti-reflective materials disclosed.

摘要翻译： 本发明提供了在半导体上制造抗反射屏障和/或抛光停止层的方法。 在半导体器件的制造期间，抗反射屏障和/或抛光 - 停止层允许更精确的光刻。 阻挡层和/或抛光 - 停止层可以包括在膜结构内具有非化学计量比的硅与氮原子的氮化物和/或氧氮化物膜。 非化学计量允许膜是半透明的，减少电磁辐射通过层的透射，从而减少电磁辐射通过光致抗蚀剂层的反射。 通过降低光致抗蚀剂材料的电磁辐射的反射，可以减少由掩模边缘衍射的影响和驻波干扰，从而允许将更精确，可再现的图案铭刻到半导体器件上。 此外，通过对用于沉积阻挡层和/或抛光 - 停止层的现有方法的简单修改，本发明的抗反射层的生产可以容易地结合到整个制造过程中，从而最小化半导体的附加成本和时间要求 制造。 本发明还包括使用所公开的抗反射材料制成的半导体器件。

公开(公告)号：US06228746B1

公开(公告)日：2001-05-08

申请号：US08993149

申请日：1997-12-18

申请人： Effiong E. Ibok

发明人： Effiong E. Ibok

IPC分类号： H01L21762

CPC分类号： H01L21/76202 ,  H01L21/76224

摘要： Methodology for achieving dual field oxide thicknesses comprises forming field oxide isolation regions to a common thickness. An oxidation barrier layer, which may comprise nitride or oxynitride, is formed on selected field oxide regions leaving others exposed. The exposed field oxide regions are enlarged in a complementary thermal oxidation step, wherein the isolation regions covered by the oxidation barrier layer are not enlarged, thereby achieving field oxide regions of at least two thicknesses.

摘要翻译： 用于实现双场氧化物厚度的方法包括将场氧化物隔离区域形成为共同的厚度。 可以在选择的场氧化物区域上形成可包含氮化物或氧氮化物的氧化阻挡层，留下其它暴露的氧化物阻挡层。 暴露的场氧化物区域在互补热氧化步骤中扩大，其中由氧化阻挡层覆盖的隔离区域不扩大，从而实现至少两个厚度的场氧化物区域。

公开(公告)号：US06391784B1

公开(公告)日：2002-05-21

申请号：US09357969

申请日：1999-07-21

申请人： Effiong E. Ibok

发明人： Effiong E. Ibok

IPC分类号： H01L21302

CPC分类号： H01L21/76224 ,  H01L21/3144

摘要： An ultranarrow insulated trench isolation structure is formed in a semiconductor substrate without creating voids in the insulating material which adversely affect the performance of finished devices. Embodiments include forming a narrow trench in the semiconductor substrate, then forming a spacer on the sidewalls of the trench, as by depositing and anisotropically etching a layer of silicon dioxide, amorphous silicon, or silicon oxynitride. The trench is then refilled as by conventional LPCVD, PECVD or HDP techniques, and the spacers are oxidized, if necessary. Since the spacers, in effect, create sloped trench walls, the trench fill can be performed, even at a high deposition rate, with substantially fewer voids than conventional processes, while also reducing reentrance of the trench walls.

摘要翻译： 在半导体衬底中形成超极化绝缘沟槽隔离结构，而不会在绝缘材料中产生不利影响成品器件性能的空隙。 实施例包括在半导体衬底中形成窄沟槽，然后通过沉积和各向异性地蚀刻二氧化硅，非晶硅或氮氧化硅层，在沟槽的侧壁上形成间隔物。 然后如常规LPCVD，PECVD或HDP技术那样重新填充沟槽，并且如果需要，间隔物被氧化。 由于间隔物实际上产生倾斜的沟槽壁，所以即使在高沉积速率下也可以执行沟槽填充，其空隙比常规工艺基本上更少，同时还减少了沟槽壁的重入。

公开(公告)号：US6051478A

公开(公告)日：2000-04-18

申请号：US992844

申请日：1997-12-18

申请人： Effiong E. Ibok

发明人： Effiong E. Ibok

IPC分类号： H01L21/762 ,  H01L49/00 ,  H01L21/76

CPC分类号： H01L21/76235

摘要： A shallow trench isolation structure is formed with a nitridated oxide liner on the sides and edges of the trench, thereby reducing interfacial strain. Embodiments include forming a trench opening in a monocrystalline silicon substrate or in an epitaxial layer formed thereon. An oxide liner is formed at the internal surface of the trench opening in a nitrous oxide ambience, creating flexible silicon-nitrogen (Si--N) bonds which relieves stress induced at the side walls and edges of the trench. The lined trench opening is then filled with an insulating material.

摘要翻译： 在沟槽的侧面和边缘上形成具有氮化氧化物衬垫的浅沟槽隔离结构，从而减少界面应变。 实施例包括在单晶硅衬底中或在其上形成的外延层中形成沟槽开口。 氧化物衬垫以一氧化二氮氛围形成在沟槽开口的内表面，产生柔性的硅 - 氮（Si-N）键，其减轻了在沟槽的侧壁和边缘处引起的应力。 然后将衬里的沟槽开口填充绝缘材料。

公开(公告)号：US5891794A

公开(公告)日：1999-04-06

申请号：US744137

申请日：1996-11-05

申请人： Effiong E. Ibok

发明人： Effiong E. Ibok

IPC分类号： H01L21/28 ,  H01L29/49 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/28035 ,  H01L29/4925

摘要： A method of manufacturing a semiconductor device to prevent uneven polysilicon gate dopant accumulation at the gate/gate oxide interface. A layer of gate oxide is formed on the surface of the silicon substrate, a layer of amorphous silicon is deposited on the gate oxide and a doped layer of amorphous silicon is deposited on the first layer. The first and second layers are deposited by chemical vapor deposition and an oxygen containing gas is selectively injected into the stream of silicon source gas depositing the first and second layers of amorphous silicon.

摘要翻译： 一种半导体器件的制造方法，用于防止在栅极/栅极氧化物界面处不均匀的多晶硅栅极掺杂剂聚集。 在硅衬底的表面上形成栅极氧化层，在栅极氧化层上沉积非晶硅层，并在第一层上沉积非晶硅的掺杂层。 通过化学气相沉积沉积第一层和第二层，并且选择性地将含氧气体注入沉积第一和第二非晶硅层的硅源气体流中。

公开(公告)号：US06319857B1

公开(公告)日：2001-11-20

申请号：US08714915

申请日：1996-09-16

申请人： Effiong E. Ibok

发明人： Effiong E. Ibok

IPC分类号： H01L21469

CPC分类号： H01L21/28185 ,  H01L21/28202 ,  H01L21/3144 ,  H01L21/3145 ,  H01L29/513 ,  H01L29/518

摘要： The present invention is an improved semiconductor device and an improved method of manufacturing a semiconductor device. The present invention deposits a layer of oxynitride where gate oxidation would normally take place. Alternatively, the method according to the present invention uses a plurality of layers of dielectric material where gate oxidation would normally take place including a layer of oxynitride having a nitrogen content. The layer of oxynitride is deposited under a predetermined pressure using a stream of gas, wherein insensitivity to defects on a surface of the substrate results from the oxynitride layer.

摘要翻译： 本发明是改进的半导体器件和制造半导体器件的改进方法。 本发明沉积一层氧氮化物，其中通常会发生栅极氧化。 或者，根据本发明的方法使用多层介电材料，其中通常会发生栅极氧化，包括具有氮含量的氮氧化物层。 使用气流在预定压力下沉积氧氮化物层，其中对氮化物层产生对衬底表面上的缺陷的不敏感性。

公开(公告)号：US6043138A

公开(公告)日：2000-03-28

申请号：US959105

申请日：1997-10-23

申请人： Effiong E. Ibok

发明人： Effiong E. Ibok

IPC分类号： H01L21/28 ,  H01L29/49 ,  H01L21/265 ,  H01L29/78

CPC分类号： H01L21/28035 ,  H01L29/4925

摘要： The present invention provides an improved semiconductor device and method of impeding the diffusion of boron by providing at least one layer of polysilicon and an interface substance. A semiconductor device according to the present invention is comprised of a substrate; gate oxide coupled to the substrate; a layer of polysilicon coupled to the gate oxide; and an interface layer between the layer of polysilicon and the gate oxide, wherein the interface layer impedes diffusion of doping material.

摘要翻译： 本发明提供一种通过提供至少一层多晶硅和界面物质来阻止硼的扩散的改进的半导体器件和方法。 根据本发明的半导体器件由衬底构成; 栅极氧化物耦合到衬底; 耦合到栅极氧化物的多晶硅层; 以及多晶硅层和栅极氧化物之间的界面层，其中界面层阻碍掺杂材料的扩散。

公开(公告)号：US5930658A

公开(公告)日：1999-07-27

申请号：US756620

申请日：1996-11-26

申请人： Effiong E. Ibok

发明人： Effiong E. Ibok

IPC分类号： H01L21/28 ,  H01L21/316 ,  H01L29/423 ,  H01L29/51 ,  H01L21/314

CPC分类号： H01L21/02164 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/28167 ,  H01L21/31662 ,  H01L29/42364 ,  H01L21/28202 ,  H01L29/518 ,  Y10S438/966

摘要： A method of manufacturing a semiconductor device to negate the effects on the device performance caused by defects on the silicon substrate. An oxygen doped amorphous silicon layer is deposited onto the gate region of the semiconductor device and can have a thickness of less than 5 nanometers. The amorphous silicon provides a conformal layer over the defects on the silicon substrate. The oxygen doping of the amorphous silicon maintains the conformality of the amorphous silicon layer during subsequent processing by preventing the formation of large amorphous silicon grains during a crystallization process. The resulting silicon oxide layer has increased uniformity and can have a thickness of less than 10 nanometers.

摘要翻译： 一种制造半导体器件以消除由硅衬底上的缺陷引起的对器件性能的影响的方法。 氧掺杂的非晶硅层沉积在半导体器件的栅极区上，并且可以具有小于5纳米的厚度。 非晶硅在硅衬底上的缺陷上提供共形层。 非晶硅的氧掺杂通过防止在结晶过程中形成大的非晶硅晶粒而在随后的加工过程中保持非晶硅层的共形性。 所得到的氧化硅层具有增加的均匀性，并且可以具有小于10纳米的厚度。

公开(公告)号：US5712196A

公开(公告)日：1998-01-27

申请号：US674081

申请日：1996-07-01

申请人： Effiong E. Ibok

发明人： Effiong E. Ibok

IPC分类号： H01L21/28 ,  H01L21/283

CPC分类号： H01L21/28052 ,  Y10S438/974

摘要： A semiconductor fabrication technique is provided for producing a low resistivity polycide. Polycide resistivity is lowered by minimizing areas where the polycide is unduly thin. By preparing the polysilicon upper surface prior to polycide formation thereon, the polysilicon surface can grow polycide at a uniform rate across the entire polysilicon surface. The polysilicon surface is prepared by either restricting doping atoms at grain boundary locations at the polysilicon surface, or by disrupting the grain boundaries by ion implanting that surface. In either instance, a properly prepared polysilicon surface greatly enhances the conductivity of polycide grown thereon.

摘要翻译： 提供半导体制造技术用于生产低电阻率的多硅化物。 通过最小化多孔体过薄的区域降低聚硅氧烷电阻率。 通过在其上形成多晶硅化合物之前制备多晶硅上表面，多晶硅表面可以在整个多晶硅表面上以均匀的速率生长多晶硅化合物。 多晶硅表面通过限制多晶硅表面的晶界位置的掺杂原子，或通过离子注入该表面来破坏晶界来制备。 在任一情况下，适当制备的多晶硅表面大大增强了其上生长的聚硅氧烷的导电性。