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    Semiconductor device wherein detection of removal of wiring triggers impairing of normal operation of internal circuit
    2.
    发明授权
    Semiconductor device wherein detection of removal of wiring triggers impairing of normal operation of internal circuit 有权
    其中检测到布线去除的半导体装置会损害内部电路的正常工作

    公开(公告)号：US06545371B1

    公开(公告)日：2003-04-08

    申请号：US09834605

    申请日：2001-04-16

    申请人： Hironori Matsumoto ,  Akihiko Nakano ,  Toshinori Ohmi ,  Eiji Yanagawa ,  Hideyuki Unno ,  Hiroshi Ban ,  Tadao Takeda

    发明人： Hironori Matsumoto ,  Akihiko Nakano ,  Toshinori Ohmi ,  Eiji Yanagawa ,  Hideyuki Unno ,  Hiroshi Ban ,  Tadao Takeda

    IPC分类号： H01L2358

    CPC分类号： H01L23/576 ,  H01L23/573 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes, on a protective film laminated on a circuit principal part, (i) a light blocking film provided so as to cover the circuit principal part, (ii) an aluminum oxide film provided so as to completely cover the light blocking film, and (iii) a light-blocking upper wiring provided on the aluminum oxide film. An attempt to exfoliate the light blocking film or the light blocking upper wiring causes the resistance-detection-use upper wiring to break or thin, thereby resulting in an increase in the resistance of the resistance-detection-use wiring. The increase in the resistance is detected by the resistance detecting circuit part, and malfunction or inoperativeness of the circuit principal part is caused in response of detection. By so doing, the circuit principal part can be protected from analysis.

    摘要翻译： 半导体器件包括在层叠在电路主要部分上的保护膜上，（i）设置成覆盖电路主要部分的遮光膜，（ii）设置成完全覆盖遮光膜的氧化铝膜 ，和（iii）设置在氧化铝膜上的遮光上层布线。 剥离遮光膜或遮光上布线的尝试使得电阻检测用上层布线断裂或变薄，从而导致电阻检测用布线的电阻增加。 通过电阻检测电路部分检测电阻的增加，并且响应于检测而引起电路主要部分的故障或不能操作。 通过这样做，可以保护电路主要部分免受分析。

    Process for preparing BiCMOS semiconductor device
    4.
    发明授权
    Process for preparing BiCMOS semiconductor device 失效
    制备BiCMOS半导体器件的工艺

    公开(公告)号：US5208171A

    公开(公告)日：1993-05-04

    申请号：US786742

    申请日：1991-11-01

    申请人： Toshinori Ohmi

    发明人： Toshinori Ohmi

    IPC分类号： H01L21/331 ,  H01L21/336 ,  H01L21/74 ,  H01L21/761 ,  H01L21/8228 ,  H01L21/8238 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/092 ,  H01L29/10

    CPC分类号： H01L29/66272 ,  H01L21/74 ,  H01L21/761 ,  H01L21/82285 ,  H01L21/823807 ,  H01L21/8249 ,  H01L29/1004 ,  H01L29/1079 ,  H01L29/66575 ,  H01L27/0928

    摘要： A process for preparing a BiCMOS semiconductor device having a MOS transistor element and a bipolar transistor element both of which are constituted in an epitaxial layer of n-type conductivity formed on a substrate of p-type conductivity, which comprises applying, after the formation of said epitaxial layer, an impurity ion of high energy simultaneously to specific of said epitaxial layer under which a channel region of said MOS transistor element and an emitter region of said bipolar transistor element are to be formed, thereby forming highly doped impurity regions around the bottom of said channel region and around the bottom of a base region of said bipolar transistor element.

    摘要翻译： 一种用于制备具有MOS晶体管元件和双极晶体管元件的BiCMOS半导体器件的方法，它们均形成在p型导电性基板上形成的n型导电体的外延层中，其包括在形成 所述外延层，高能量的杂质离子同时到所述外延层的特定区域，在所述外延层上形成所述MOS晶体管元件的沟道区域和所述双极晶体管元件的发射极区域，由此在底部附近形成高掺杂杂质区域 并且围绕所述双极晶体管元件的基极区域的底部。

    Integrated semiconductor circuit device having Schottky barrier diode
    5.
    发明授权
    Integrated semiconductor circuit device having Schottky barrier diode 失效
    具有肖特基势垒二极管的集成半导体电路器件

    公开(公告)号：US06791154B2

    公开(公告)日：2004-09-14

    申请号：US10054823

    申请日：2002-01-25

    申请人： Hironori Matsumoto ,  Toshinori Ohmi

    发明人： Hironori Matsumoto ,  Toshinori Ohmi

    IPC分类号： H01L31108

    CPC分类号： H01L27/0629

    摘要： An integrated semiconductor circuit device comprising a diode bridge circuit formed of a Schottky barrier diode and a periphery circuit formed of a MOS transistor which are formed on a single silicon substrate, wherein a Schottky barrier, which is a component of the Schottky barrier diode, is made of a silicide layer.

    摘要翻译： 一种集成半导体电路器件，包括由肖特基势垒二极管形成的二极管电桥电路和由形成在单个硅衬底上的MOS晶体管形成的外围电路，其中作为肖特基势垒二极管的分量的肖特基势垒为 由硅化物层制成。

    Semiconductor device and method of manufacturing same
    6.
    发明授权
    Semiconductor device and method of manufacturing same 失效
    半导体装置及其制造方法

    公开(公告)号：US5959330A

    公开(公告)日：1999-09-28

    申请号：US904557

    申请日：1997-08-04

    申请人： Norihiro Tokuyama ,  Toshinori Ohmi ,  Alberto Oscar Adan

    发明人： Norihiro Tokuyama ,  Toshinori Ohmi ,  Alberto Oscar Adan

    IPC分类号： H01L21/76 ,  H01L21/265 ,  H01L21/336 ,  H01L21/762 ,  H01L29/08 ,  H01L29/78 ,  H01L29/76

    CPC分类号： H01L29/66575 ,  H01L21/76216 ,  H01L29/0847

    摘要： After a field oxide film is formed on a P-type semiconductor substrate, ion implantation of boron is carried out with respect to a whole surface of the substrate so that a channel stopper layer is formed. Then, a MOS FET is formed in an active region of the semiconductor substrate. Subsequently, ion implantation of phosphorus is carried out, by using a gate electrode of the MOS FET and the field oxide film as a mask, so that impurity layers which have the same type of conductivity as that of the channel stopper layer and has a concentration lower than that of the channel stopper layer are formed right under the source/drain regions of the MOS FET between the source/drain regions and the channel stopper layer.

    摘要翻译： 在P型半导体衬底上形成场氧化膜之后，相对于衬底的整个表面进行硼的离子注入，形成沟道阻挡层。 然后，在半导体衬底的有源区中形成MOS FET。 随后，通过使用MOS FET的栅电极和场氧化膜作为掩模来进行磷的离子注入，使得具有与沟道阻挡层相同类型的导电性并具有浓度的杂质层 低于沟道阻挡层的栅极/漏极区域的正下方位于源极/漏极区域和沟道阻挡层之间的MOS FET的源极/漏极区域的正下方。