公开(公告)号：US06759722B2

公开(公告)日：2004-07-06

申请号：US09820671

申请日：2001-03-30

申请人： Eiji Yanagawa ,  Akihiko Nakano ,  Toshinori Ohmi ,  Hironori Matsumoto ,  Tadao Takeda ,  Hideyuki Unno ,  Hiroshi Ban

发明人： Eiji Yanagawa ,  Akihiko Nakano ,  Toshinori Ohmi ,  Hironori Matsumoto ,  Tadao Takeda ,  Hideyuki Unno ,  Hiroshi Ban

IPC分类号： H01L2982

CPC分类号： H01L23/573 ,  H01L23/58 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L29/0657 ,  H01L2224/13144 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/07811 ,  H01L2924/10158 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19043 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： In the present semiconductor device, a chip with an LSI circuit is secured to a board 3 (with the chip flipped) so as to be level. The LSI circuit on the chip is specified to operate normally only when the chip is level. Further, the back of the chip is processed so as to give stress to the chip. The chip has a reduced thickness of 50 &mgr;m or less (alternatively 30 &mgr;m to 50 &mgr;m). Therefore, when the chip is detached from the board, it deforms and is no longer level due to the stress, which prohibits the LSI circuit from operating normally. This way, the present semiconductor device ensures that no analysis can be conducted on the LSI circuit once the chip is detached.

摘要翻译： 在本半导体器件中，具有LSI电路的芯片被固定在板3上（芯片翻转）以使其水平。 指定芯片上的LSI电路只在芯片处于电平状态时正常工作。 此外，芯片的背面被加工成对芯片施加压力。 该芯片具有减小的厚度为50μm或更小（或者30μm至50μm）。 因此，当芯片与板分离时，其变形并且由于应力而不再水平，这阻止了LSI电路正常工作。 这样，本半导体装置确保一旦芯片脱离就不能对LSI电路进行分析。

公开(公告)号：US06545371B1

公开(公告)日：2003-04-08

申请号：US09834605

申请日：2001-04-16

申请人： Hironori Matsumoto ,  Akihiko Nakano ,  Toshinori Ohmi ,  Eiji Yanagawa ,  Hideyuki Unno ,  Hiroshi Ban ,  Tadao Takeda

发明人： Hironori Matsumoto ,  Akihiko Nakano ,  Toshinori Ohmi ,  Eiji Yanagawa ,  Hideyuki Unno ,  Hiroshi Ban ,  Tadao Takeda

IPC分类号： H01L2358

CPC分类号： H01L23/576 ,  H01L23/573 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes, on a protective film laminated on a circuit principal part, (i) a light blocking film provided so as to cover the circuit principal part, (ii) an aluminum oxide film provided so as to completely cover the light blocking film, and (iii) a light-blocking upper wiring provided on the aluminum oxide film. An attempt to exfoliate the light blocking film or the light blocking upper wiring causes the resistance-detection-use upper wiring to break or thin, thereby resulting in an increase in the resistance of the resistance-detection-use wiring. The increase in the resistance is detected by the resistance detecting circuit part, and malfunction or inoperativeness of the circuit principal part is caused in response of detection. By so doing, the circuit principal part can be protected from analysis.

摘要翻译： 半导体器件包括在层叠在电路主要部分上的保护膜上，（i）设置成覆盖电路主要部分的遮光膜，（ii）设置成完全覆盖遮光膜的氧化铝膜 ，和（iii）设置在氧化铝膜上的遮光上层布线。 剥离遮光膜或遮光上布线的尝试使得电阻检测用上层布线断裂或变薄，从而导致电阻检测用布线的电阻增加。 通过电阻检测电路部分检测电阻的增加，并且响应于检测而引起电路主要部分的故障或不能操作。 通过这样做，可以保护电路主要部分免受分析。

公开(公告)号：US06472730B1

公开(公告)日：2002-10-29

申请号：US09551741

申请日：2000-04-18

申请人： Eiji Yanagawa ,  Akihiko Nakano ,  Toshinori Ohmi ,  Tadao Takeda ,  Hideyuki Unno ,  Hiroshi Ban

发明人： Eiji Yanagawa ,  Akihiko Nakano ,  Toshinori Ohmi ,  Tadao Takeda ,  Hideyuki Unno ,  Hiroshi Ban

IPC分类号： H01L23495

CPC分类号： H01L23/573 ,  H01L23/49503 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L29/0657 ,  H01L2224/32057 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10157 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor device in accordance with the present invention includes a semiconductor element chip pressed and secured on a distortion die-pad so that the semiconductor element chip, sealed inside a package, is held in a predetermined distorted state. The predetermined distorted state is preferably downward or upward warping. The semiconductor element chip operates normally in the distorted state, and does not operate normally when the semiconductor element chip is separated from the semiconductor device, and thereby released from the distortion and laid alone. This ensures that the semiconductor element chip is protected from circuit analysis.

摘要翻译： 根据本发明的半导体器件包括被压紧并固定在失真裸片上的半导体元件芯片，使得密封在封装内的半导体元件芯片保持在预定的失真状态。 预定的扭曲状态优选为向下或向上翘曲。 半导体元件芯片在失真状态下正常工作，并且当半导体元件芯片与半导体器件分离时，其不能正常工作，从而从失真中释放并放置。 这确保半导体元件芯片免受电路分析。

公开(公告)号：US6060773A

公开(公告)日：2000-05-09

申请号：US74437

申请日：1998-05-07

申请人： Hiroshi Ban ,  Masaaki Tanno ,  Tadao Takeda

发明人： Hiroshi Ban ,  Masaaki Tanno ,  Tadao Takeda

IPC分类号： H01L21/306 ,  H01L23/58 ,  H01L23/02

CPC分类号： H01L23/573 ,  H01L21/30608 ,  H01L2924/0002 ,  Y10S257/922

摘要： A semiconductor chip has a nonvolatile memory formed on the upper surface side of a semiconductor substrate. The chip includes at least one recess portion formed in the lower surface of the semiconductor substrate. The recess portion is located in a region corresponding to the nonvolatile memory. A method of manufacturing the semiconductor chip is also disclosed.

摘要翻译： 半导体芯片具有在半导体衬底的上表面侧形成的非易失性存储器。 芯片包括形成在半导体衬底的下表面中的至少一个凹部。 凹部位于与非易失性存储器对应的区域中。 还公开了制造半导体芯片的方法。

公开(公告)号：US4629843A

公开(公告)日：1986-12-16

申请号：US719376

申请日：1985-04-03

申请人： Namio Kato ,  Tadao Takeda

发明人： Namio Kato ,  Tadao Takeda

IPC分类号： H05B6/12

CPC分类号： H05B6/1245 ,  H05B6/1254 ,  H05B2206/022 ,  Y02B40/126

摘要： An induction cooking apparatus or a ceramics hob which heats conductive food and/or a conductive pan through hysteresis loss and/or eddy current loss by exciting a coil with high frequency power, comprises a casing, a coil mounted on a coil support, and an insulation cover plate between the coil and food to be cooked. The coil support is made of ferro-magnetic material of mixture of insulation resin and ferrite powder which occupies 75-85 weight %, instead of a prior mere insulation resin so that no flux leaks below the coil support. Preferably, the coil support has a plurality of longitudinal ferrite ribs extending radially under the coil support, and still preferably, the coil support has a plurality of holes at the central portion of the same so that permeability at the central portion is essentially smaller than that at the outer portion to provide uniform flux.

摘要翻译： 一种感应烹调设备或陶瓷炉，其通过激发具有高频功率的线圈的滞后损耗和/或涡流损耗来加热导电食物和/或导电盘，包括壳体，安装在线圈支架上的线圈和 线圈之间的绝缘盖板和待烹饪的食物。 线圈支架由绝缘树脂和铁氧体粉末混合物的铁磁材料制成，占75-85重量％，而不是以前的纯绝缘树脂，使得线圈支架下面的焊剂不会泄漏。 优选地，线圈支架具有在线圈支撑件下径向延伸的多个纵向铁氧体肋，并且优选地，线圈支撑件在其中心部分处具有多个孔，使得中心部分处的磁导率基本上小于 在外部以提供均匀的通量。

公开(公告)号：US06598137B1

公开(公告)日：2003-07-22

申请号：US09541086

申请日：2000-03-31

申请人： Kazuhiro Yaegawa ,  Ryuichi Ogawa ,  Tadao Takeda ,  Hiroki Suto ,  Masaaki Tanno

发明人： Kazuhiro Yaegawa ,  Ryuichi Ogawa ,  Tadao Takeda ,  Hiroki Suto ,  Masaaki Tanno

IPC分类号： G06F1200

CPC分类号： G06F9/4403

摘要： A 1-chip microcomputer having a built-in nonvolatile memory includes at least one erasable flash memory provided in a memory space of the microcomputer, a boot ROM for storing an initial program to start up the 1-chip microcomputer and a transfer program to transfer the initial program to the flash memory, and control means for, when the flash memory stores no program, transferring the initial program to the flash memory in accordance with the transfer program and subsequently removing the boot ROM from the memory space. Consequently, even if a new program is additionally stored to the nonvolatile memory in the 1-chip microcomputer, the additional program can be carried out.

摘要翻译： 具有内置非易失性存储器的1片式微型计算机包括设置在微型计算机的存储器空间中的至少一个可擦除闪存，用于存储启动单片微机的初始程序的引导ROM和传送程序 闪速存储器的初始程序，以及控制装置，用于当闪速存储器不存储程序时，根据传送程序将初始程序传送到闪速存储器，随后从存储器空间中移除引导ROM。 因此，即使将新程序另外存储到单片微型计算机的非易失性存储器中，也可以执行附加程序。

公开(公告)号：US06934884B1

公开(公告)日：2005-08-23

申请号：US09568683

申请日：2000-05-11

申请人： Masaki Wakabayashi ,  Kazuhiro Yaegawa ,  Masaaki Tanno ,  Hiroki Suto ,  Tadao Takeda

发明人： Masaki Wakabayashi ,  Kazuhiro Yaegawa ,  Masaaki Tanno ,  Hiroki Suto ,  Tadao Takeda

IPC分类号： G06K19/07 ,  G01R31/3183 ,  G06F11/22 ,  G06F11/26 ,  G06F11/267 ,  G06F15/78 ,  G06F11/00

CPC分类号： G01R31/318335 ,  G01R31/318385 ,  G01R31/318392 ,  G06F11/2236 ,  G06F11/2273

摘要： In order to provide a built-in self testing function, a one-chip microcomputer is equipped with an activation register for activating the test operation and a built-in self test activation pattern generator for setting initial values at test control circuits (pseudo random number generator, logical circuit testing compressor, pattern generator, and memory testing compressor). In accordance with an instruction from the CPU, a built-in self test is activated so that the results of tests of the memory and the group of logical circuits are read from the memory testing compressor and the logical circuit testing compressor, and respectively compared with expected values preliminarily stored in the memory in the one-chip microcomputer; thus, the results are diagnosed. Thus, it is possible to carry out a built-in self test without using a plurality of exclusively-used test terminals.

摘要翻译： 为了提供内置的自检功能，单片机配备有用于激活测试操作的激活寄存器和内置的自检激活模式发生器，用于设置测试控制电路的初始值（伪随机数 发电机，逻辑电路测试压缩机，模式发生器和内存测试压缩机）。 根据CPU的指令，激活内置自检，使存储器和逻辑电路组的测试结果从存储器测试压缩器和逻辑电路测试压缩器读取，并分别与 初步存储在单片机中的存储器中的预期值; 因此，诊断结果。 因此，可以在不使用多个专用测试端子的情况下进行内置自检。

公开(公告)号：US5989981A

公开(公告)日：1999-11-23

申请号：US886876

申请日：1997-07-02

申请人： Sadao Nakashima ,  Terukazu Ohno ,  Toshiaki Tsuchiya ,  Tetsushi Sakai ,  Shinji Nakamura ,  Takemi Ueki ,  Yuichi Kado ,  Tadao Takeda

发明人： Sadao Nakashima ,  Terukazu Ohno ,  Toshiaki Tsuchiya ,  Tetsushi Sakai ,  Shinji Nakamura ,  Takemi Ueki ,  Yuichi Kado ,  Tadao Takeda

IPC分类号： H01L21/265 ,  H01L21/322

CPC分类号： H01L21/3226 ,  H01L21/26533

摘要： A method of manufacturing an SOI substrate uses an SOI substrate having a first single-crystal silicon layer, an insulating layer formed on the first single-crystal silicon layer, and a second single-crystal silicon layer formed on the insulating layer. The surface of the second single-crystal silicon layer is thermally oxidized. The second single-crystal silicon layer is controlled to have a predetermined thickness by removing the thermally oxidized surface. This step controlling the second single-crystal silicon layer to have a predetermined thickness includes the step of eliminating, by annealing, a stacking fault formed by the thermal oxidation.

摘要翻译： 制造SOI衬底的方法使用具有第一单晶硅层，形成在第一单晶硅层上的绝缘层和形成在绝缘层上的第二单晶硅层的SOI衬底。 第二单晶硅层的表面被热氧化。 通过去除热氧化表面，将第二单晶硅层控制为具有预定的厚度。 控制第二单晶硅层具有预定厚度的步骤包括通过退火消除由热氧化形成的堆垛层错的步骤。

公开(公告)号：US07213117B2

公开(公告)日：2007-05-01

申请号：US09805199

申请日：2001-03-14

申请人： Masaki Wakabayashi ,  Ryuichi Ogawa ,  Kazuhiro Yaegawa ,  Susumu Kurioka ,  Kenji Ohno ,  Tadao Takeda ,  Hiroki Sutou ,  Masahiro Yoshizawa

发明人： Masaki Wakabayashi ,  Ryuichi Ogawa ,  Kazuhiro Yaegawa ,  Susumu Kurioka ,  Kenji Ohno ,  Tadao Takeda ,  Hiroki Sutou ,  Masahiro Yoshizawa

IPC分类号： G06F12/14

CPC分类号： H04Q3/64 ,  H04M3/51 ,  H04M2201/06 ,  H04M2201/34 ,  H04M2201/36 ,  H04M2201/38 ,  H04Q11/0471 ,  H04Q2213/13003 ,  H04Q2213/1305 ,  H04Q2213/1307 ,  H04Q2213/13072 ,  H04Q2213/13095 ,  H04Q2213/13103 ,  H04Q2213/13106 ,  H04Q2213/13209 ,  H04Q2213/13305 ,  H04Q2213/1332 ,  H04Q2213/13322

摘要： A 1-chip microcomputer of the present invention has (a) a monitor flag for setting a flag indicating that a specified address space is accessed, (b) an access permission address range setting register, for setting an address range in which an access is permitted while the flag is set, (c) an access permission area detection circuit for judging whether the access is made within the address range thus set, (d) an access permission setting register, for setting whether or not an access with respect to an address other than the address range should be permitted, and (e) memory read-out control circuit and memory writing control circuit for controlling an access with respect to a nonvolatile memory based on a result thus judged and content set by the access permission setting register. With the arrangement, it is possible to provide a 1-chip microcomputer that maintains the security among application programs.

摘要翻译： 本发明的1片微型计算机具有（a）用于设定表示指定的地址空间被访问的标志的监视标志，（b）访问许可地址范围设定寄存器，用于设定访问权限的地址范围 （c）用于判断在如此设置的地址范围内是否进行访问的访问允许区域检测电路，（d）访问许可设置寄存器，用于设置是否访问相对于 应允许地址范围以外的地址，以及（e）存储器读出控制电路和存储器写入控制电路，用于基于由此判断的结果来控制对非易失性存储器的访问，以及由访问许可设置寄存器设置的内容 。 通过这种布置，可以提供一种在应用程序之间保持安全性的1片微型计算机。

公开(公告)号：US06981179B1

公开(公告)日：2005-12-27

申请号：US09552701

申请日：2000-04-19

申请人： Haruhiko Shigemasa ,  Kazuhiro Yaegawa ,  Masaaki Tanno ,  Nobuhiro Shimoyama ,  Tadao Takeda

发明人： Haruhiko Shigemasa ,  Kazuhiro Yaegawa ,  Masaaki Tanno ,  Nobuhiro Shimoyama ,  Tadao Takeda

IPC分类号： G06F12/16 ,  B42D15/10 ,  G01R31/319 ,  G06F11/22 ,  G06F11/26 ,  G06F11/273 ,  G06F15/78 ,  G06K19/07 ,  G06K19/073 ,  G06K19/077 ,  G11C29/52 ,  G06F11/00

CPC分类号： G06F11/2635 ,  G01R31/31926 ,  G06K7/0095 ,  G06K19/07 ,  G06K19/073 ,  G11C29/52

摘要： When a built-in nonvolatile memory in a microcomputer is tested, a control program prestored in a boot ROM is run upon entering a test command from an external communication device; a test program is transferred from the external communication device to a built-in RAM through a communication circuit; a control of a CPU is switched to the built-in RAM after the test program has been transferred and a test is conducted on the nonvolatile memory; and a test result and a fail log are transferred to the external communication device through the communication circuit. Consequently, the built-in nonvolatile memory in the microcomputer can be checked without leaving the test program on the chip.

摘要翻译： 当测试微型计算机中的内置非易失性存储器时，预先存储在引导ROM中的控制程序在从外部通信设备输入测试命令时运行; 通过通信电路将测试程序从外部通信设备传送到内置RAM; 在传送测试程序并对非易失性存储器进行测试之后，将CPU的控制切换到内置RAM; 并且通过通信电路将测试结果和故障日志传送到外部通信设备。 因此，可以检查微型计算机中的内置非易失性存储器，而不将测试程序留在芯片上。