公开(公告)号：US07551465B2

公开(公告)日：2009-06-23

申请号：US11741462

申请日：2007-04-27

申请人： Tecla Ghilardi ,  Paolo Tessariol ,  Giorgio Servalli ,  Alessandro Grossi ,  Angelo Visconti ,  Emilio Camerlenghi

发明人： Tecla Ghilardi ,  Paolo Tessariol ,  Giorgio Servalli ,  Alessandro Grossi ,  Angelo Visconti ,  Emilio Camerlenghi

IPC分类号： G11C5/02 ,  G11C7/02

CPC分类号： G11C16/28

摘要： A reference cell layout includes a plurality of active areas, in parallel to each other, and a first contact of the active areas, and a first gate, the first contact shorting the active areas. A memory device includes the reference cell layout and a corresponding array of memory cells having active areas sized substantially identical to the active areas of the reference cell layout and plural second contacts respectively contacting the active areas of the memory cells.

摘要翻译： 参考单元布局包括彼此并联的多个有效区域和有源区域的第一接触，以及第一栅极，第一接触部使有源区域短路。 存储器件包括参考单元格布局和相应的存储器单元阵列，其存储单元阵列具有大小与参考单元布局的有效区域基本相同的有效区域，以及分别接触存储单元的有效区域的多个第二触点。

公开(公告)号：US06420223B2

公开(公告)日：2002-07-16

申请号：US09730518

申请日：2000-12-05

申请人： Emilio Camerlenghi

发明人： Emilio Camerlenghi

IPC分类号： H01L218238

CPC分类号： H01L27/105 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11534

摘要： A process for forming floating gate non-volatile memory cells in a cell matrix with associated control circuitry comprising both N-channel and P-channel MOS transistors is provided. The process includes forming active areas in a substrate for the cell matrix and the associated control circuitry. A first thin oxide layer and a first polysilicon layer are deposited on the active areas to produce floating gate regions of the memory cells, and a second dielectric layer is deposited on the active areas. A second polysilicon layer is then deposited on the active areas. A masking and etching step is performed for exposing the substrate for the associated control circuitry followed by the deposition of a third polysilicon layer. The third polysilicon layer is defined to produce the gate regions of the transistors for the associated control circuitry while the third polysilicon layer is removed from the cell matrix. A self-aligned etching step is performed to define the gate regions of the memory cells, and dopants are implanted in the junction areas to produce the source/drain regions of the memory cells.

摘要翻译： 提供了一种用于在具有包括N沟道和P沟道MOS晶体管的相关控制电路的单元矩阵中形成浮栅非易失性存储单元的过程。 该过程包括在用于单元矩阵和相关联的控制电路的衬底中形成有源区。 第一薄氧化物层和第一多晶硅层沉积在有源区上以产生存储单元的浮动栅区，并且第二介电层沉积在有源区上。 然后将第二多晶硅层沉积在有源区上。 执行掩模和蚀刻步骤，用于暴露相关控制电路的衬底，随后沉积第三多晶硅层。 第三多晶硅层被定义为产生用于相关联的控制电路的晶体管的栅极区域，而第三多晶硅层从单元矩阵中移除。 执行自对准蚀刻步骤以限定存储器单元的栅极区域，并且在结区域中注入掺杂剂以产生存储器单元的源极/漏极区域。

公开(公告)号：US6124169A

公开(公告)日：2000-09-26

申请号：US999403

申请日：1997-12-29

申请人： Emilio Camerlenghi ,  Paolo Caprara ,  Gabriella Fontana

发明人： Emilio Camerlenghi ,  Paolo Caprara ,  Gabriella Fontana

IPC分类号： H01L21/28 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L21/76897 ,  H01L21/76838 ,  H01L2924/3011

摘要： A process creates contacts in semiconductor electronic devices and in particular on bit lines of non-volatile memories with cross-point structure. The cross-point structure includes memory cell matrices in which the bit lines are parallel unbroken diffusion strips extending along a column of the matrix with the contacts being provided through associated contact apertures defined through a dielectric layer deposited over a contact region defined on a semiconductor substrate at one end of the bit lines. The process calls for a step of implantation and following diffusion of contact areas provided in the substrate at opposite sides of each bit line to be contacted to widen the area designed to receive the contacts.

摘要翻译： 一种工艺在半导体电子器件中产生触点，特别是在具有交叉点结构的非易失性存储器的位线上。 交叉点结构包括存储单元矩阵，其中位线是沿着矩阵的列延伸的平行的不间断扩散条，触点通过相关联的接触孔提供，该接触孔通过沉积在限定在半导体衬底上的接触区域上的电介质层 在位线的一端。 该过程需要植入步骤，并且在每个位线的相对侧处设置在衬底中的接触区域扩散以便扩大被设计用于接收触点的区域。

公开(公告)号：US5659516A

公开(公告)日：1997-08-19

申请号：US368211

申请日：1995-01-03

申请人： Giulio Casagrande ,  Emilio Camerlenghi

发明人： Giulio Casagrande ,  Emilio Camerlenghi

IPC分类号： G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30 ,  G11C13/00

CPC分类号： G11C16/30 ,  G11C5/147

摘要： A voltage regulator for electrically programmable non-volatile semiconductor memory devices of the type comprising a gain stage (3), supplied by a programming voltage (Vpp) and having an input terminal connected to a divider (6) of said programming voltage (Vpp) and an output terminal (U) connected to a programming line (5) of at least one memory cell (2) comprises at least one circuit element (4) capable of adapting the line programming voltage (5) to the length (L) of the memory cell (2). This provides a drain voltage, on the bit line of the memory device, which varies according to the actual length of the memory cell.

摘要翻译： 一种用于电可编程非易失性半导体存储器件的电压调节器，包括由编程电压（Vpp）提供并具有连接到所述编程电压（Vpp）的分压器（6）的输入端的增益级（3） 以及连接到至少一个存储单元（2）的编程线（5）的输出端（U）包括至少一个电路元件（4），其能够将线路编程电压（5）适应于 存储单元（2）。 这提供了存储器件的位线上的漏极电压，其根据存储器单元的实际长度而变化。

公开(公告)号：US08211762B1

公开(公告)日：2012-07-03

申请号：US12512907

申请日：2009-07-30

申请人： Emilio Camerlenghi ,  Giulio Albini

发明人： Emilio Camerlenghi ,  Giulio Albini

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/4763

CPC分类号： H01L29/7881 ,  H01L27/11521

摘要： Briefly, embodiments of non-volatile memory and embodiments of fabrication thereof are disclosed. For example, a non-volatile memory device having a gate assembly with a floating gate and a control gate assembly is described. The control gate assembly includes a non-metal conductive control gate and a metal control gate in one embodiment. Additional embodiments are described, including use of a sacrificial nitride layer and forming contact recesses to create source or drain contacts, as other examples.

摘要翻译： 简而言之，公开了非易失性存储器的实施例及其制造的实施例。 例如，描述了具有带有浮动栅极和控制栅极组件的栅极组件的非易失性存储器件。 在一个实施例中，控制门组件包括非金属导电控制栅极和金属控制栅极。 描述了另外的实施例，包括使用牺牲氮化物层和形成接触凹部来产生源极或漏极接触，如其他示例。

公开(公告)号：US20070202647A1

公开(公告)日：2007-08-30

申请号：US11647504

申请日：2006-12-27

申请人： Marcello Mariani ,  Emilio Camerlenghi ,  Emanuele Concari

发明人： Marcello Mariani ,  Emilio Camerlenghi ,  Emanuele Concari

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/40114

摘要： Non volatile memory cells are integrated on a semiconductor substrate, each cell comprising a floating gate electrode. These cells are made by depositing at least one protective layer on the semiconductor substrate, forming a first plurality of openings in the protective layer, etching the semiconductor substrate through the first plurality of openings so as to form a plurality of trenches, filling in the plurality of trenches and the first plurality of openings with an insulation layer, etching surface portions of the protective layer to form: surface portions of the insulation layer projecting from the semiconductor substrate divided from each other by a second plurality of openings, and lower portions of the protection layer confined below the second plurality of openings, etching the insulation layer to reduce the cross dimensions of the surface portions of the insulation layer, removing the lower portions of said protection layer until the semiconductor substrate is exposed.

摘要翻译： 非易失性存储器单元集成在半导体衬底上，每个单元包括浮置栅电极。 这些电池通过在半导体衬底上沉积至少一个保护层而形成，在保护层中形成第一多个开口，通过第一多个开口蚀刻半导体衬底，以形成多个沟槽，填充多个 的沟槽和具有绝缘层的第一多个开口，蚀刻保护层的表面部分以形成：通过第二多个开口彼此分隔的从半导体衬底突出的绝缘层的表面部分，以及 保护层限制在第二多个开口下方，蚀刻绝缘层以减小绝缘层的表面部分的横截面尺寸，去除所述保护层的下部直到半导体衬底露出。

公开(公告)号：US06380582B2

公开(公告)日：2002-04-30

申请号：US09528406

申请日：2000-03-17

申请人： Emilio Camerlenghi ,  Elio Colabella ,  Luca Pividori ,  Adriana Rebora

发明人： Emilio Camerlenghi ,  Elio Colabella ,  Luca Pividori ,  Adriana Rebora

IPC分类号： H01L2976

CPC分类号： H01L27/11521 ,  H01L21/3213 ,  H01L21/76838

摘要： Self-aligned etching process for providing a plurality of mutually parallel word lines in a first conducting layer deposited over a plagiarized architecture obtained starting from a semiconductor substrate on which is provided a plurality of active elements extending along separate parallel lines e.g., memory cell bit lines and comprising gate regions made up of a first conducting layer, an intermediate dielectric layer and a second conducting layer with said regions being insulated from each other by insulation regions to form said architecture with said word lines being defined photolithographically by protective strips implemented by means of: a vertical profile etching for complete removal from the unprotected areas of the first conducting layer of the second conducting layer and of the intermediate dielectric layer respectively, and a following isotropic etching of the first conducting layer.

摘要翻译： 自对准蚀刻工艺，用于在从半导体衬底开始沉积的剽窃结构上沉积的第一导电层中提供多个相互平行的字线，其上设置有沿着分离的并行线延伸的多个有源元件，例如存储器单元位线 并且包括由第一导电层，中间电介质层和第二导电层构成的栅极区，其中所述区域通过绝缘区域彼此绝缘以形成所述结构，所述字线通过防护带光刻地限定， ：用于从第二导电层和中间介电层的第一导电层的未保护区域完全去除的垂直轮廓刻蚀，以及第一导电层的以下各向同性蚀刻。

公开(公告)号：US06222245B1

公开(公告)日：2001-04-24

申请号：US08739997

申请日：1996-10-30

申请人： Roberto Bez ,  Emilio Camerlenghi

发明人： Roberto Bez ,  Emilio Camerlenghi

IPC分类号： H01L2900

CPC分类号： H01L28/40 ,  H01L29/94

摘要： The invention relates to a high-capacitance capacitor which is monolithically integratable on a semiconductor substrate doped with a first type of dopant and accommodating a diffusion well which is doped with a second type of dopant and has a first active region formed therein. A layer of gate oxide is deposited over the diffusion well which is covered with a first layer of polycrystalline silicon and separated from a second layer of polycrystalline silicon by an interpoly dielectric layer. Advantageously, the high-capacitance capacitor of the invention includes a first elementary capacitor having the first and second layers of polycrystalline silicon as its conductive plates, and the interpoly dielectric layer as the isolation dielectric, and a second elementary capacitor having the first layer of polycrystalline silicon and the diffusion well as its conductive plates and the gate oxide layer as the isolation dielectric.

摘要翻译： 本发明涉及一种高容量电容器，该高容量电容器可单独集成在掺杂有第一类掺杂剂的半导体衬底上，并且容纳掺杂有第二类掺杂剂的扩散阱，并且其中形成有第一有源区。 栅极氧化物沉积在扩散阱上，该扩散阱被第一多晶硅层覆盖，并通过多晶硅介电层与第二多晶硅层分离。有利的是，本发明的大容量电容器包括具有 第一和第二层多晶硅作为其导电板，并且作为隔离电介质的多晶硅绝缘层，以及具有第一层多晶硅和扩散阱作为其导电板的第二基本电容器，以及作为隔离层的栅极氧化物层 电介质。

公开(公告)号：US5576990A

公开(公告)日：1996-11-19

申请号：US367538

申请日：1995-01-03

申请人： Emilio Camerlenghi ,  Giulio Casagrande

发明人： Emilio Camerlenghi ,  Giulio Casagrande

IPC分类号： G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30 ,  G11C11/34

CPC分类号： G11C5/147 ,  G11C16/30

摘要： A voltage regulator for electrically programmable non-volatile semiconductor memory devices of the type comprising a gain stage (3), supplied by a programming voltage (V.sub.PP) and having an input terminal connected to a divider (6) of said programming voltage (V.sub.PP) and an output terminal (U) connected to a programming line (5) of at least one memory cell (2) comprises at least one circuit element (4) capable of adapting the line programming voltage (5) to the length (L) of the memory cell (2). This solution makes it possible to have on the bit line of the memory device a drain voltage varying according to the actual length of the memory cell.

摘要翻译： 一种用于电可编程非易失性半导体存储器件的电压调节器，包括由编程电压（VPP）提供并具有连接到所述编程电压（VPP）的分压器（6）的输入端的增益级（3） 以及连接到至少一个存储单元（2）的编程线（5）的输出端（U）包括至少一个电路元件（4），其能够将线路编程电压（5）适应于 存储单元（2）。 该解决方案使得可以在存储器件的位线上具有根据存储器单元的实际长度而变化的漏极电压。

公开(公告)号：US06537879B2

公开(公告)日：2003-03-25

申请号：US09900501

申请日：2001-07-06

申请人： Roberto Bez ,  Emilio Camerlenghi ,  Stefano Ratti

发明人： Roberto Bez ,  Emilio Camerlenghi ,  Stefano Ratti

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A process for fabricating non-volatile memory cells on a semiconductor substrate includes forming a stack structure comprised of a first polysilicon layer isolated from the substrate by an oxide layer. The first polysilicon layer, oxide layer, and semiconductor substrate are cascade etched to define a first portion of a floating gate region of the cell and at least one trench bordering an active area of the memory cell. The at least one trench is filled with an isolation layer. The process further includes depositing a second polysilicon layer onto the whole exposed surface of the semiconductor, and etching the second polysilicon layer to expose the floating gate region formed in the first polysilicon layer, thereby forming extensions adjacent the above portion of the first polysilicon layer.