Mobile device prevention of contactless card attacks
    2.
    发明授权
    Mobile device prevention of contactless card attacks 有权
    移动设备防止非接触式卡攻击

    公开(公告)号:US09379841B2

    公开(公告)日:2016-06-28

    申请号:US14431034

    申请日:2014-11-17

    Abstract: Technologies related to mobile device prevention of contactless card attacks are generally described. In some examples, a mobile computing device may monitor for electromagnetic signals at frequencies used for short range communications with contactless cards. Detection of such electromagnetic signals by the mobile computing device may indicate an attack attempt on a proximal contactless card. In response to detection of such electromagnetic signals, the mobile computing device may automatically generate a disruption signal effective to disrupt communications between contactless card readers and any proximal contactless cards, to thereby foil the attack before sensitive contactless card data is stolen.

    Abstract translation: 通常描述与非接触式卡攻击的移动设备防止相关的技术。 在一些示例中,移动计算设备可以在用于与非接触式卡进行短距离通信的频率下监视电磁信号。 由移动计算设备检测这样的电磁信号可以指示对近侧非接触式卡的攻击尝试。 响应于这种电磁信号的检测,移动计算设备可以自动产生有效地中断非接触式读卡器与任何近侧非接触式卡之间的通信的中断信号,从而在敏感的非接触式卡数据被盗之前消除攻击。

    Dynamic reconfiguration of programmable hardware
    3.
    发明授权
    Dynamic reconfiguration of programmable hardware 有权
    可编程硬件的动态重新配置

    公开(公告)号:US09361416B2

    公开(公告)日:2016-06-07

    申请号:US13994882

    申请日:2013-01-30

    CPC classification number: G06F17/5054

    Abstract: Technologies related to dynamic reconfiguration of programmable hardware are generally described. In some examples, coprocessor regions in programmable hardware such as a Field Programmable Gate Array (FPGA) may be dynamically assigned to transition the FPGA from a starting arrangement of coprocessor regions to an efficient arrangement. A placement algorithm may be executed to determine the efficient arrangement, and a path finding algorithm may be executed to determine path finding operations leading from the starting arrangement to the efficient arrangement. The path finding operations may be performed to implement the transition.

    Abstract translation: 通常描述与可编程硬件的动态重新配置相关的技术。 在一些示例中,诸如现场可编程门阵列(FPGA)的可编程硬件中的协处理器区域可以被动态分配以将FPGA从协处理器区域的启动布置转换到有效的布置。 可以执行放置算法以确定有效的布置,并且可以执行路径查找算法以确定从起始布置到有效布置的路径查找操作。 可以执行路径查找操作以实现转换。

    VIRTUAL MACHINE PLACEMENT
    4.
    发明申请
    VIRTUAL MACHINE PLACEMENT 有权
    虚拟机配置

    公开(公告)号:US20160285906A1

    公开(公告)日:2016-09-29

    申请号:US14665726

    申请日:2015-03-23

    CPC classification number: G06F9/45558 G06F2009/4557 G06F2009/45591

    Abstract: Technologies for virtual machine placement within a data center are described herein. An example method may include determining a shared threat potential for a virtual machine based, at least in part, on a degree of co-location the virtual machine has with a current virtual machine operating on a physical machine, determining a workload threat potential for the virtual machine based, at least in part, on a level of advantage associated with placing the virtual machine on the physical machine, determining a threat potential for the virtual machine based, at least in part, on a combination of the shared threat potential and the workload threat potential, and placing the virtual machine on the physical machine based on the threat potential.

    Abstract translation: 本文描述了数据中心内的虚拟机放置技术。 至少部分地基于虚拟机与在物理机器上操作的当前虚拟机的共位度确定虚拟机的共享威胁潜力,确定用于虚拟机的工作负载威胁潜力的示例性方法可以包括: 至少部分地基于将所述虚拟机放置在所述物理机器上的优点级别来确定所述虚拟机的威胁潜力,所述威胁潜力至少部分地基于共享威胁潜力和所述虚拟机的组合, 工作负载威胁潜力,并将虚拟机置于基于威胁潜力的物理机上。

    SECURE SYSTEM TIME REPORTING
    5.
    发明申请
    SECURE SYSTEM TIME REPORTING 有权
    安全系统时间报告

    公开(公告)号:US20140123139A1

    公开(公告)日:2014-05-01

    申请号:US13877216

    申请日:2012-10-25

    Abstract: Technologies related to secure system time reporting are generally described. In some examples, responses to some system time requests may be manipulated to prevent leaking information that may be of interest for timing attacks, while responses to other system time requests need not be manipulated. In particular, responses to system time requests that are separated from a previous system time request by a predetermined minimum value, or less, may be manipulated. Responses to system time requests that are separated from a previous system time request by more than the predetermined minimum value need not be manipulated. Furthermore, secure system time reporting may be adaptively deployed to servers in a data center on an as-needed basis.

    Abstract translation: 通常描述与安全系统时间报告相关的技术。 在一些示例中,可以操纵对某些系统时间请求的响应,以防止对于定时攻击可能感兴趣的泄露信息,而不需要操纵对其他系统时间请求的响应。 特别地,可以操纵对与先前系统时间请求分离预定最小值或更小的系统时间请求的响应。 对与先前的系统时间请求分离超过预定最小值的系统时间请求的响应不需要被操纵。 此外,安全系统时间报告可以根据需要自适应地部署到数据中心中的服务器。

    Acceleration benefit estimator
    6.
    发明授权

    公开(公告)号:US09747185B2

    公开(公告)日:2017-08-29

    申请号:US13850671

    申请日:2013-03-26

    Inventor: Kevin Fine

    Abstract: Technologies related to acceleration benefit estimation are generally described. In some examples, data centers may identify applications that may benefit from Programmable Hardware Accelerators (PHAs), and test the identified applications by running accelerated versions thereof, i.e., versions that use one or more identified PHAs, and comparing performance of the accelerated versions to reference versions, i.e., versions that do not use the one or more identified PHAs. Data centers may report comparison results may be reported to data center customers to encourage customer adoption of PHAs.

    Secure system time reporting
    7.
    发明授权
    Secure system time reporting 有权
    安全的系统时间报告

    公开(公告)号:US09195492B2

    公开(公告)日:2015-11-24

    申请号:US13877216

    申请日:2012-10-25

    Abstract: Technologies related to secure system time reporting are generally described. In some examples, responses to some system time requests may be manipulated to prevent leaking information that may be of interest for timing attacks, while responses to other system time requests need not be manipulated. In particular, responses to system time requests that are separated from a previous system time request by a predetermined minimum value, or less, may be manipulated. Responses to system time requests that are separated from a previous system time request by more than the predetermined minimum value need not be manipulated. Furthermore, secure system time reporting may be adaptively deployed to servers in a data center on an as-needed basis.

    Abstract translation: 通常描述与安全系统时间报告相关的技术。 在一些示例中,可以操纵对某些系统时间请求的响应,以防止对于定时攻击可能感兴趣的泄露信息,而不需要操纵对其他系统时间请求的响应。 特别地,可以操纵对与先前系统时间请求分离预定最小值或更小的系统时间请求的响应。 对与先前的系统时间请求分离超过预定最小值的系统时间请求的响应不需要被操纵。 此外,安全系统时间报告可以根据需要自适应地部署到数据中心中的服务器。

    Virtual machine placement
    8.
    发明授权

    公开(公告)号:US09965309B2

    公开(公告)日:2018-05-08

    申请号:US14665726

    申请日:2015-03-23

    CPC classification number: G06F9/45558 G06F2009/4557 G06F2009/45591

    Abstract: Technologies for virtual machine placement within a data center are described herein. An example method may include determining a shared threat potential for a virtual machine based, at least in part, on a degree of co-location the virtual machine has with a current virtual machine operating on a physical machine, determining a workload threat potential for the virtual machine based, at least in part, on a level of advantage associated with placing the virtual machine on the physical machine, determining a threat potential for the virtual machine based, at least in part, on a combination of the shared threat potential and the workload threat potential, and placing the virtual machine on the physical machine based on the threat potential.

    MASKING POWER USAGE OF CO-PROCESSORS ON FIELD-PROGRAMMABLE GATE ARRAYS
    10.
    发明申请
    MASKING POWER USAGE OF CO-PROCESSORS ON FIELD-PROGRAMMABLE GATE ARRAYS 有权
    在现场可编程门阵列上掩蔽合作处理器的电力使用

    公开(公告)号:US20140237284A1

    公开(公告)日:2014-08-21

    申请号:US13978877

    申请日:2013-01-31

    CPC classification number: G06F9/455 G06F21/00 G06F21/556 Y04S40/24

    Abstract: Technologies are generally described for masking power usage of co-processors on field-programmable gate arrays. In some examples, one or more moat brick circuits may be implemented around a co-processor loaded on a held-programmable gate array (FPGA). The moat brick circuits may be configured to use negative feedback and/or noise to mask the power usage variations of the co-processor from other co-processors on the FPGA.

    Abstract translation: 通常描述技术来掩蔽现场可编程门阵列上的协处理器的功率使用。 在一些示例中,可以在加载在可编程门阵列(FPGA)上的协处理器周围实现一个或多个护城河砖电路。 护城河砖电路可以被配置为使用负反馈和/或噪声来掩蔽来自FPGA上的其他协处理器的协处理器的功率使用变化。

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