公开(公告)号：US4486674A

公开(公告)日：1984-12-04

申请号：US510852

申请日：1983-07-05

申请人： Eric D. Neely

发明人： Eric D. Neely

IPC分类号： H03K19/013 ,  H03K19/082 ,  H03K19/088

CPC分类号： H03K19/0136 ,  H03K19/0826

摘要： A three state gate having an output capable of assuming an active high, an active low, or a high impedance state is disclosed that has an enhanced transition from the active high to the active low. An output means includes a first transistor for supplying current to the output and a second transistor for sinking current from the output. A phase splitter means coupled to the output means determines the conductivity of the first and second transistors. An input means is responsive to an input signal and controls the phase splitter means. An output enable means is provided that disables both the first and second transistors for providing the high impedance output. A feedback means for enhancing the downward transition of the output signal from an active high to an active low includes a feedback transistor having a base connected to a supply voltage terminal by a resistor which can be used to vary the speed of the downward transition. A diode is coupled between the collector of the feedback transistor and the output terminal. The feedback transistor is reverse biased, except when the output signal is transitioning from the active high to the active low. A second diode is coupled between the base of the first output transistor and the collector of the feedback transistor for discharging stored base-collector capacitance of the first output transistor.

摘要翻译： 公开了具有能够呈现有效高电平，有源低电平或高阻抗状态的输出的三态门，其具有从有源高电平向有源低电平的增强的转变。 输出装置包括用于向输出端提供电流的第一晶体管和用于从输出端吸收电流的第二晶体管。 耦合到输出装置的相位分离器装置确定第一和第二晶体管的电导率。 输入装置响应输入信号并控制分相装置。 提供一种输出使能装置，其禁止第一和第二晶体管两者提供高阻抗输出。 用于增强输出信号从有效高电平向有效低电平的向下转换的反馈装置包括具有通过电阻器连接到电源电压端子的基极的反馈晶体管，其可以用于改变向下转换的速度。 二极管耦合在反馈晶体管的集电极和输出端之间。 反馈晶体管是反向偏置的，除了当输出信号从有效高电平转换为低电平有效时。 第二二极管耦合在第一输出晶体管的基极和反馈晶体管的集电极之间，用于对第一输出晶体管的存储的基极集电极电容进行放电。

公开(公告)号：US5432462A

公开(公告)日：1995-07-11

申请号：US54495

申请日：1993-04-30

申请人： Carlos D. Obregon ,  Michael A. Wells ,  Eric D. Neely

发明人： Carlos D. Obregon ,  Michael A. Wells ,  Eric D. Neely

IPC分类号： H03K19/0175 ,  H03K19/00 ,  H03K19/0185 ,  H03K19/08

CPC分类号： H03K19/0016 ,  H03K19/018521

摘要： The present invention includes an input buffer circuit (10) having sleep mode and bus hold capability. An input section (11) of the buffer circuit is operated from an operating voltage which is lower than a supply voltage of the buffer circuit thereby minimizing the static power dissipation. Sleep mode circuitry (15, 36, 38) is included for effectively disconnecting an input signal from the rest of the buffer circuit thereby minimizing dynamic power dissipation. Bus hold circuitry (40) is included for holding the logic state appearing at an output of the input buffer circuit when the input signal is removed thereby further reducing the static power dissipation.

摘要翻译： 本发明包括具有睡眠模式和总线保持能力的输入缓冲电路（10）。 缓冲电路的输入部分（11）从低于缓冲电路的电源电压的工作电压进行操作，从而使静态功耗最小化。 包括休眠模式电路（15,36,38），用于有效地将输入信号与缓冲电路的其余部分断开，从而使动态功耗最小化。 包括总线保持电路（40），用于当输入信号被去除时保持出现在输入缓冲器电路的输出端的逻辑状态，从而进一步降低静态功耗。

公开(公告)号：US5546021A

公开(公告)日：1996-08-13

申请号：US194974

申请日：1994-02-14

申请人： Daniel T. Bizuneh ,  Carlos Obregon ,  Michael A. Wells ,  Eric D. Neely

发明人： Daniel T. Bizuneh ,  Carlos Obregon ,  Michael A. Wells ,  Eric D. Neely

IPC分类号： H03K19/0175 ,  G06F13/40

CPC分类号： G06F13/4072 ,  Y02B60/1228 ,  Y02B60/1235

摘要： A 3 state BiCMOS output buffer (100) with power down capability has been provided. The buffer includes an input stage (102), responsive to an input signal, an output coupled to both a pull-up driver (114), and an output pull-down driver (116) wherein the drivers provide an output signal at an output of the buffer in response to the input signal. Additionally, the buffer includes a power down sense circuit (108), coupled to a power supply node (118), for turning off an output pull-up transistor (214) when the power supply node is powered down and thus eliminating leakage paths within the buffer. The buffer also includes a noise limiting circuit (112) for slowing down a high to low transition at the output of the buffer thereby reducing the switching noise of the buffer while not affecting the overall speed of the buffer.

摘要翻译： 已经提供了具有掉电能力的3状态BiCMOS输出缓冲器（100）。 缓冲器包括响应于输入信号的输入级（102），耦合到上拉驱动器（114）和输出下拉驱动器（116）的输出，其中驱动器在输出端提供输出信号 的缓冲器响应输入信号。 此外，缓冲器包括耦合到电源节点（118）的断电检测电路（108），用于在电源节点断电时关闭输出上拉晶体管（214），从而消除输出上拉晶体管 缓冲区。 缓冲器还包括用于在缓冲器的输出端缓慢降低高转变到低转换的噪声限制电路（112），从而在不影响缓冲器的整体速度的情况下降低缓冲器的开关噪声。

公开(公告)号：US4745308A

公开(公告)日：1988-05-17

申请号：US467681

申请日：1983-02-18

申请人： Eric D. Neely

发明人： Eric D. Neely

IPC分类号： H03K19/003 ,  H03K19/082 ,  H03K17/16 ,  H03K19/084 ,  H03K19/088

CPC分类号： H03K19/00353 ,  H03K19/0823

摘要： A three state gate having an output capable of assuming an active high, an active low, or a high impedance state is disclosed that eliminates a glitch in the output during the transition from the high impedance state to an active high. An output means includes a first transistor for supplying current to the output and a second transistor for draining current from the output. A phase splitting means determines the conductivity of the first and second transistors. A logic means is responsive to both an input signal and an output enable signal and is coupled to the phase splitting means. The logic means includes a level setting means that insures that the second transistor is not conductive during the transition of the output from the active high to the high impedance state.

摘要翻译： 公开了具有能够呈现有效高电平，有效低电平或高阻抗状态的输出的三态门，其消除了在从高阻抗状态向高电平跃迁期间的输出中的毛刺。 输出装置包括用于向输出端提供电流的第一晶体管和用于从输出引出电流的第二晶体管。 相位分离装置确定第一和第二晶体管的电导率。 逻辑装置响应输入信号和输出使能信号两者并耦合到相位分离装置。 逻辑装置包括电平设置装置，其确保在输出从有效高电平转换到高阻抗状态期间第二晶体管不导通。

公开(公告)号：US4424455A

公开(公告)日：1984-01-03

申请号：US370711

申请日：1982-04-22

申请人： Eric D. Neely

发明人： Eric D. Neely

IPC分类号： H03K5/151 ,  H03K19/007 ,  H03K19/01

CPC分类号： H03K5/1515

摘要： A data selection circuit selectively generates first and second complementary signals in response to an input signal so as to enable specific data paths and disable others. The circuit includes a non-inverting portion which generates an output signal having the same sense as the input signal, and an inverting portion which inverts the input signal. Since the non-inverting portion has an extra inverting stage within it, a diode is coupled between the inverting portion and the true output for steering base drive away from the inverting portion when the input signal makes a low to high transition. In this manner, the inverting output is prevented from going low until the non-inverting goes high.

摘要翻译： 数据选择电路响应于输入信号选择性地产生第一和第二互补信号，以使能特定数据路径并禁用其他信号。 该电路包括产生具有与输入信号相同感测的输出信号的非反相部分和使输入信号反相的反相部分。 由于非反相部分在其内部具有额外的反相级，所以当输入信号进入低到高转变时，二极管耦合在反相部分和转换器底座驱动器的真实输出端之间，使其转向远离反相部分。 以这种方式，反相输出被防止变低，直到非反相变高。

公开(公告)号：US5287021A

公开(公告)日：1994-02-15

申请号：US880109

申请日：1992-05-06

申请人： Carlos D. Obregon ,  Eric D. Neely ,  Michael A. Wells

发明人： Carlos D. Obregon ,  Eric D. Neely ,  Michael A. Wells

IPC分类号： H03K19/003 ,  H03K17/60 ,  H03K17/16 ,  H03K19/02 ,  H03K19/20

CPC分类号： H03K19/00346

摘要： A plurality of transistors (22, 23, 27) are utilized to provide a low noise high-to-low transition (40) on an output (19) of a circuit (10). The transistors (22, 23, 27) are sequentially enabled to vary a rate of change of output current thereby minimizing noise created by the high-to-low transition (40). A first transistor (22) is enabled to provide a low rate of change. Subsequently, a second transistor (23) is enabled to provide a higher rate of change. Then, just prior to disabling the second transistor (23) a third transistor (27) is enabled to provide a d.c. level.

摘要翻译： 多个晶体管（22,23,27）用于在电路（10）的输出（19）上提供低噪声的高到低的转换（40）。 晶体管（22,23,27）依次使能以改变输出电流的变化率，从而最小化由高到低的转变产生的噪声（40）。 第一晶体管（22）能够提供低变化率。 随后，第二晶体管（23）能够提供更高的变化率。 然后，在禁止第二晶体管（23）之前，第三晶体管（27）能够提供直流 水平。

公开(公告)号：US5027010A

公开(公告)日：1991-06-25

申请号：US417137

申请日：1989-10-04

申请人： Eric D. Neely ,  Perng Hsyng

发明人： Eric D. Neely ,  Perng Hsyng

IPC分类号： H03K19/013 ,  H03K19/018 ,  H03K19/088

CPC分类号： H03K19/088 ,  H03K19/013 ,  H03K19/01806

摘要： A TTL output driver is provided which increases the high level of the output signal thereof. The first and second emitters of a first transistor are coupled to the collector and base of a second transistor, respectively, the emitter and collector of which are coupled to the output of the TTL output driver and through a series combination of diode and resistor to a source of operating potential respectively. The output voltage is increased by reducing the base current drive of the first transistor required to achieve the desired output current.

摘要翻译： 提供TTL输出驱动器，其增加其输出信号的高电平。 第一晶体管的第一和第二发射极分别耦合到第二晶体管的集电极和基极，其发射极和集电极耦合到TTL输出驱动器的输出，并通过二极管和电阻器的串联组合到 营运潜力来源分别。 通过减少实现所需输出电流所需的第一晶体管的基极电流驱动来增加输出电压。

公开(公告)号：US4467223A

公开(公告)日：1984-08-21

申请号：US370706

申请日：1982-04-22

申请人： Eric D. Neely

发明人： Eric D. Neely

IPC分类号： H03K19/00 ,  H03K19/082 ,  H03K17/60 ,  H03K19/088

CPC分类号： H03K19/0826 ,  H03K19/001

摘要： A circuit for providing a signal which enables the high impedance state of a subsequent three state circuit includes a first circuit portion which provides current to an output node to disable the high impedance state when an input signal is in the first state and a second circuit portion which sinks current from the output node to enable the high impedance state when the input signal is in a second state. The circuit includes an input stage which is directly coupled to a transistor, which transistor simultaneously enables said second circuit portion and disables said first circuit portion when the input signal switches from said second state to said first state.

摘要翻译： 用于提供使后续三态电路的高阻抗状态的信号的电路包括：第一电路部分，当输入信号处于第一状态时，向输出节点提供电流以禁止高阻抗状态;以及第二电路部分 其在输入信号处于第二状态时从输出节点吸收电流以使能高阻抗状态。 电路包括直接耦合到晶体管的输入级，该晶体管同时使能所述第二电路部分，并且当输入信号从所述第二状态切换到所述第一状态时禁用所述第一电路部分。