公开(公告)号：US5958019A

公开(公告)日：1999-09-28

申请号：US674328

申请日：1996-07-01

申请人： Erik E. Hagersten ,  Robert C. Zak, Jr. ,  Shaw-Wen Yang ,  Aleksandr Guzovskiy ,  William A. Nesheim ,  Monica C. Wong-Chan ,  Hien Nguyen

发明人： Erik E. Hagersten ,  Robert C. Zak, Jr. ,  Shaw-Wen Yang ,  Aleksandr Guzovskiy ,  William A. Nesheim ,  Monica C. Wong-Chan ,  Hien Nguyen

IPC分类号： G06F9/52 ,  G06F9/46 ,  G06F12/08 ,  G06F13/42

CPC分类号： G06F9/52 ,  G06F12/0828

摘要： When a processor within a computer system performs a synchronization operation, the system interface within the node delays subsequent transactions from the processor until outstanding coherency activity is completed. Therefore, the computer system may employ asynchronous operations. The synchronization operations may be used when needed to guarantee global completion of one or more prior asynchronous operations. In one embodiment, the synchronization operation is placed into a queue within the system interface. When the synchronization operation reaches the head of the queue, it may be initiated within the system interface. The system interface further includes a request agent comprising multiple control units, each of which may concurrently service coherency activity with respect to a different transaction. Furthermore, the system interface includes a synchronization control vector register which stores a bit for each control unit. Upon initiation of the synchronization operation within the system interface, bits corresponding to those control units which are performing coherency activity (i.e. those which are not idle) are set while other bits are cleared. As each control unit returns to the idle state, the corresponding bit is cleared as well. Once all the bits within the synchronization control vector register are cleared, the coherency activity which was outstanding when the synchronization operation was initiated is complete. The synchronization operation may then be completed.

摘要翻译： 当计算机系统内的处理器执行同步操作时，节点内的系统接口会延迟来自处理器的后续事务，直到完成一致的一致性活动。 因此，计算机系统可以采用异步操作。 当需要保证一个或多个在先的异步操作的全局完成时，可以使用同步操作。 在一个实施例中，同步操作被放置在系统接口内的队列中。 当同步操作到达队列的头部时，可以在系统界面内启动。 该系统接口还包括一个包含多个控制单元的请求代理，每个控制单元可以相对于不同的事务同时提供一致性活动。 此外，系统接口包括存储每个控制单元的位的同步控制向量寄存器。 在系统接口中启动同步操作之后，在执行一致性活动的那些控制单元（即那些不空闲的）的对应的位被设置，而其它位被清除。 当每个控制单元返回到空闲状态时，相应的位也被清除。 一旦清除了同步控制向量寄存器中的所有位，完成了同步操作启动时未完成的一致性活动。 然后可以完成同步操作。

公开(公告)号：US5862316A

公开(公告)日：1999-01-19

申请号：US674276

申请日：1996-07-01

申请人： Erik E. Hagersten ,  John R. Catenzaro ,  William A. Nesheim ,  Monica C. Wong-Chan ,  Robert C. Zak, Jr. ,  Paul N. Loewenstein

发明人： Erik E. Hagersten ,  John R. Catenzaro ,  William A. Nesheim ,  Monica C. Wong-Chan ,  Robert C. Zak, Jr. ,  Paul N. Loewenstein

IPC分类号： G06F11/34 ,  G06F11/00 ,  G06F11/22 ,  G06F12/08

CPC分类号： G06F11/2205 ,  Y10S707/99952

摘要： Protocol agents involved in the performance of global coherency activity detect errors with respect to the activity being performed. The errors are logged by a computer system such that diagnostic software may be executed to determine the error detected and to trace the error to the erring software or hardware. In particular, information regarding the first error to be detected is logged. Subsequent errors may receive more or less logging depending upon programmable configuration values. Additionally, those errors which receive full logging may be programmably selected via error masks. The protocol agents each comprise multiple independent state machines which independently process requests. If the request which a particular state machine is processing results in an error, the particular state machine may enter a freeze state. Information regarding the request which is collected by the state machine may thereby be saved for later access. A state machine freezes upon detection of the error if a maximum number of the multiple state machines are not already frozen and the aforementioned error mask indicates that full error logging is employed for the detected error. Therefore, at least a minimum number of the multiple state machines remain functioning even in the presence of a large number of errors. Still further, prior to entering the freeze state, the protocol state machines may transition through a recovery state in which resources not used for error logging purposes are freed from the erring request.

摘要翻译： 参与执行全局一致性活动的协议代理检测相对于正在执行的活动的错误。 这些错误由计算机系统记录，使得可以执行诊断软件以确定检测到的错误并将错误跟踪到错误的软件或硬件。 特别地，记录关于要检测的第一错误的信息。 随后的错误可能会根据可编程的配置值接收或多或少的记录。 此外，可以通过错误掩码可编程地选择接收完整日志记录的错误。 协议代理各自包括独立处理请求的多个独立状态机。 如果特定状态机正在处理的请求导致错误，则特定状态机可能进入冻结状态。 关于由国家机器收集的关于请求的信息可以被保存以供稍后访问。 如果多个状态机的最大数量尚未冻结，并且上述错误掩码表示对于检测到的错误采用全错误记录，则状态机将在检测到错误后冻结。 因此，即使存在大量错误，至少多个状态机的最小数量也保持运行。 此外，在进入冻结状态之前，协议状态机可以转换到恢复状态，其中不用于错误记录的资源的资源从错误请求中解除。

公开(公告)号：US06219775B1

公开(公告)日：2001-04-17

申请号：US09040747

申请日：1998-03-18

申请人： Jon P. Wade ,  Daniel R. Cassiday ,  Robert D. Lordi ,  Guy Lewis Steele, Jr. ,  Margaret A. St. Pierre ,  Monica C. Wong-Chan ,  Zahi S. Abuhamdeh ,  David C. Douglas ,  Mahesh N. Ganmukhi ,  Jeffrey V. Hill ,  W. Daniel Hillis ,  Scott J. Smith ,  Shaw-Wen Yang ,  Robert C. Zak, Jr.

发明人： Jon P. Wade ,  Daniel R. Cassiday ,  Robert D. Lordi ,  Guy Lewis Steele, Jr. ,  Margaret A. St. Pierre ,  Monica C. Wong-Chan ,  Zahi S. Abuhamdeh ,  David C. Douglas ,  Mahesh N. Ganmukhi ,  Jeffrey V. Hill ,  W. Daniel Hillis ,  Scott J. Smith ,  Shaw-Wen Yang ,  Robert C. Zak, Jr.

IPC分类号： G06F702

CPC分类号： G06F15/8092 ,  G06F15/17381 ,  G06F15/8084 ,  G06F21/52

摘要： A massively-parallel computer includes a plurality of processing nodes and at least one control node interconnected by a network. The network faciliates the transfer of data among the processing nodes and of commands from the control node to the processing nodes. Each processing node includes an interface for transmitting data over, and receiving data and commands from, the network, at least one memory module for storing data, a node processor and an auxiliary processor. The node processor receives commands received by the interface and processes data in response thereto, in the process generating memory access requests for facilitating the retrieval of data from or storage of data in the memory module. The node processor further controlling the transfer of data over the network by the interface. The auxiliary processor is connected to the memory module and the node processor. In response to memory access requests from the node processor, the auxiliary processor performs a memory access operation to store data received from the node processor in the memory module, or to retrieve data from the memory module for transfer to the node processor. In response to auxiliary processing instructions from the node processor, the auxiliary processor performs data processing operations in connection with data in the memory module.

摘要翻译： 大型并行计算机包括多个处理节点和由网络互连的至少一个控制节点。 该网络便于处理节点之间的数据传输和从控制节点到处理节点的命令。 每个处理节点包括用于在网络上传输数据并从其接收数据和命令的接口，用于存储数据的至少一个存储器模块，节点处理器和辅助处理器。 节点处理器在产生存储器访问请求的过程中接收由接口接收的命令并响应于此处理数据，以便于从存储器模块中的数据检索或存储数据。 节点处理器进一步通过接口控制网络上的数据传输。 辅助处理器连接到存储器模块和节点处理器。 响应于来自节点处理器的存储器访问请求，辅助处理器执行存储器访问操作以将从节点处理器接收的数据存储在存储器模块中，或者从存储器模块检索数据以传送到节点处理器。 响应于来自节点处理器的辅助处理指令，辅助处理器结合存储器模块中的数据执行数据处理操作。

公开(公告)号：US5872987A

公开(公告)日：1999-02-16

申请号：US714635

申请日：1996-09-16

申请人： Jon P. Wade ,  Daniel R. Cassiday ,  Robert D. Lordi ,  Guy Lewis Steele, Jr. ,  Margaret A. St. Pierre ,  Monica C. Wong-Chan ,  Zahi S. Abuhamdeh ,  David C. Douglas ,  Mahesh N. Ganmukhi ,  Jeffrey V. Hill ,  W. Daniel Hillis ,  Scott J. Smith ,  Shaw-Wen Yang ,  Robert C. Zak, Jr.

发明人： Jon P. Wade ,  Daniel R. Cassiday ,  Robert D. Lordi ,  Guy Lewis Steele, Jr. ,  Margaret A. St. Pierre ,  Monica C. Wong-Chan ,  Zahi S. Abuhamdeh ,  David C. Douglas ,  Mahesh N. Ganmukhi ,  Jeffrey V. Hill ,  W. Daniel Hillis ,  Scott J. Smith ,  Shaw-Wen Yang ,  Robert C. Zak, Jr.

IPC分类号： G06F15/173 ,  G06F15/78 ,  G06F15/80 ,  G06F7/02

CPC分类号： G06F15/8092 ,  G06F15/17381 ,  G06F15/8084 ,  G06F21/52

摘要： A massively-parallel computer includes a plurality of processing nodes and at least one control node interconnected by a network. The network faciliates the transfer of data among the processing nodes and of commands from the control node to the processing nodes. Each each processing node includes an interface for transmitting data over, and receiving data and commands from, the network, at least one memory module for storing data, a node processor and an auxiliary processor. The node processor receives commands received by the interface and processes data in response thereto, in the process generating memory access requests for facilitating the retrieval of data from or storage of data in the memory module. The node processor further controlling the transfer of data over the network by the interface. The auxiliary processor is connected to the memory module and the node processor. In response to memory access requests from the node processor, the auxiliary processor performs a memory access operation to store data received from the node processor in the memory module, or to retrieve data from the memory module for transfer to the node processor. In response to auxiliary processing instructions from the node processor, the auxiliary processor performs data processing operations in connection with data in the memory module.

摘要翻译： 大型并行计算机包括多个处理节点和由网络互连的至少一个控制节点。 该网络便于处理节点之间的数据传输和从控制节点到处理节点的命令。 每个处理节点包括用于从网络传输数据并从其接收数据和命令的接口，用于存储数据的至少一个存储器模块，节点处理器和辅助处理器。 节点处理器在产生存储器访问请求的过程中接收由接口接收的命令并响应于此处理数据，以便于从存储器模块中的数据检索或存储数据。 节点处理器进一步通过接口控制网络上的数据传输。 辅助处理器连接到存储器模块和节点处理器。 响应于来自节点处理器的存储器访问请求，辅助处理器执行存储器访问操作以将从节点处理器接收的数据存储在存储器模块中，或者从存储器模块检索数据以传送到节点处理器。 响应于来自节点处理器的辅助处理指令，辅助处理器结合存储器模块中的数据执行数据处理操作。

公开(公告)号：US5752258A

公开(公告)日：1998-05-12

申请号：US672946

申请日：1996-07-01

申请人： Aleksandr Guzovskiy ,  Robert C. Zak, Jr. ,  Mark Bromley

发明人： Aleksandr Guzovskiy ,  Robert C. Zak, Jr. ,  Mark Bromley

IPC分类号： G06F12/08

CPC分类号： G06F12/0826

摘要： A directory system directs cache line access requests from processors in a multi-processor system with a shared memory system through a cache line states directory. The cache line states directory stores a state value that identifies a cache line shared states word. The cache line shared states word identifies the processor that owns the cache line and the state of access of each processor that shares access to the cache line. A state value encoder encodes a cache line shared state word into a state value and loads the state value into the cache line states directory. A state value decoder decodes the state value into a cache line shared state word for use by the cache line directory system in retrieving the cache line. A plurality of cache line tables are used with each cache line assigned to one of the tables. The cache line table stores a state value for each cache line shared states word stored in the table. The encoder and decoder perform a table look-up to convert between a cache line shared state word and a state value. Each of said cache line tables stores an ordered list of cache line shared state words and their corresponding state values. The ordered list is a list of cache line shared state words that have the most significance to the multi-processor system.

摘要翻译： 目录系统通过高速缓存行状态目录指向具有共享存储器系统的多处理器系统中的处理器的缓存线路访问请求。 缓存行状态目录存储一个标识高速缓存行共享状态字的状态值。 高速缓存行共享状态字标识拥有高速缓存行的处理器以及共享对高速缓存行访问的每个处理器的访问状态。 状态值编码器将高速缓存行共享状态字编码为状态值，并将状态值加载到高速缓存行状态目录中。 状态值解码器将状态值解码为高速缓存行共享状态字，以供高速缓存行目录系统在检索高速缓存行时使用。 使用多个高速缓存行表，每个高速缓存行分配给其中一个表。 高速缓存行表存储表中存储的每个高速缓存行共享状态字的状态值。 编码器和解码器执行表查找以在高速缓存行共享状态字和状态值之间进行转换。 每个所述高速缓存行表存储高速缓存线共享状态字及其相应状态值的有序列表。 有序列表是对多处理器系统最重要的高速缓存行共享状态字的列表。

公开(公告)号：US07233538B1

公开(公告)日：2007-06-19

申请号：US10909705

申请日：2004-08-02

申请人： Chung-Hsiao R. Wu ,  Robert C. Zak, Jr.

发明人： Chung-Hsiao R. Wu ,  Robert C. Zak, Jr.

IPC分类号： G11C7/00

CPC分类号： G11C29/02 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40626 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/5002 ,  G11C2211/4061

摘要： A method and apparatus for controlling a DRAM refresh rate. In one embodiment, a computer system includes a memory subsystem having a memory controller and one or more DRAM (dynamic random access memory) devices. The memory controller is configured to periodically initiate a refresh cycle to the one or more DRAM devices. The memory controller is also configured to monitor the temperature of the one or more DRAM devices. If the temperature exceeds a preset threshold, the memory controller is configured to increase the rate at which the periodic refresh cycle is performed.

摘要翻译： 一种用于控制DRAM刷新率的方法和装置。 在一个实施例中，计算机系统包括具有存储器控制器和一个或多个DRAM（动态随机存取存储器）设备的存储器子系统。 存储器控制器被配置为周期性地向一个或多个DRAM设备发起刷新周期。 存储器控制器还被配置为监视一个或多个DRAM器件的温度。 如果温度超过预设阈值，则存储器控制器被配置为增加执行周期性刷新周期的速率。

公开(公告)号：US5926829A

公开(公告)日：1999-07-20

申请号：US005058

申请日：1998-01-09

申请人： Erik Hagersten ,  Robert C. Zak, Jr.

发明人： Erik Hagersten ,  Robert C. Zak, Jr.

IPC分类号： G06F12/08 ,  G06F13/14

CPC分类号： G06F12/0813 ,  G06F12/0811 ,  G06F12/0817 ,  G06F2212/2542 ,  G06F2212/272

摘要： The present invention provides a hybrid Non-Uniform Memory Architecture (NUMA) and Cache-Only Memory Architecture (COMA) caching architecture together with a cache-coherent protocol for a computer system having a plurality of sub-systems coupled to each other via a system interconnect. In one implementation, each sub-system includes at least one processor, a page-oriented COMA cache and a line-oriented hybrid NUMA/COMA cache. Such a hybrid system provides flexibility and efficiency in caching both large and small, and/or sparse and packed data structures. Each sub-system is able to independently store data in COMA mode or in NUMA mode. When caching in COMA mode, a sub-system allocates a page of memory space and then stores the data within the allocated page in its COMA cache. Depending on the implementation, while caching in COMA mode, the sub-system may also store the same data in its hybrid cache for faster access. Conversely, when caching in NUMA mode, the sub-system stores the data, typically a line of data, in its hybrid cache.

公开(公告)号：US07225383B1

公开(公告)日：2007-05-29

申请号：US09487529

申请日：2000-01-19

申请人： David Wood ,  Robert C. Zak, Jr. ,  Monica Wong-Chan ,  Christopher J. Jackson ,  Thomas P. Webber ,  Mark D. Hill

发明人： David Wood ,  Robert C. Zak, Jr. ,  Monica Wong-Chan ,  Christopher J. Jackson ,  Thomas P. Webber ,  Mark D. Hill

IPC分类号： G06F11/00

CPC分类号： G06F13/4265 ,  Y10S707/99931

摘要： An apparatus and method for resending a request in a computer system using a delay value is provided. In response to receiving a request, a target device in a computer system may detect that it is temporarily unable to process the request. The target device can send a response to the sending device to indicate that it is temporarily unavailable. The response can include a delay value that can provide a hint to the sending device as to when to resend the request. The target device may generate the delay value according to the type of condition that is causing it to be temporarily unavailable. The delay value may be generated according to a static heuristic or a dynamic algorithm based on previous temporarily unavailable conditions. The delay value may also be used by an error recovery mechanism where a sending device exceeds a retry limit for a particular request.

摘要翻译： 提供了一种使用延迟值在计算机系统中重新发送请求的装置和方法。 响应于接收到请求，计算机系统中的目标设备可以检测到它暂时不能处理请求。 目标设备可以向发送设备发送响应，以指示它暂时不可用。 响应可以包括可以向发送设备提供关于何时重新发送请求的提示的延迟值。 目标设备可以根据导致其暂时不可用的条件类型来生成延迟值。 可以根据基于先前临时不可用条件的静态启发式或动态算法生成延迟值。 延迟值还可以由发送设备超过特定请求的重试限制的错误恢复机制使用。

公开(公告)号：US5388214A

公开(公告)日：1995-02-07

申请号：US183219

申请日：1994-01-14

申请人： Charles E. Leiserson ,  Robert C. Zak, Jr. ,  W. Daniel Hillis ,  Bradley C. Kuszmaul ,  Jeffrey V. Hill

发明人： Charles E. Leiserson ,  Robert C. Zak, Jr. ,  W. Daniel Hillis ,  Bradley C. Kuszmaul ,  Jeffrey V. Hill

IPC分类号： G06F15/16 ,  G06F11/00 ,  G06F11/08 ,  G06F11/22 ,  G06F15/173 ,  G06F15/80 ,  G06F13/00

CPC分类号： G06F15/17381 ,  G06F11/08 ,  G06F11/22 ,  G06F11/324 ,  G06F15/17343 ,  H04L45/48 ,  H04L49/35 ,  H04L49/555 ,  G06F2201/88

摘要： A computer comprising a plurality of processing nodes, a control node and a request distribution network. Each processing node receives processing requests and generates in response processed data. The control node generates processing requests for transfer to selected ones of the processing nodes as identified by associated request address information, and receives processed data in response, the request address information identifying selected ones of the processing nodes to receive a processing request in parallel. The request distribution network distributes the processing requests to the processing nodes and returns processed data to the control node. The network includes a plurality of request distribution nodes connected in a plurality of levels to form a tree-structure, including an upper root level and a lower leaf level. Each request distribution node is connected to receive processing requests from, and to couple processed data to, a parent, the parent of the request distribution node of the root level comprising the control node, and each request distribution node being further connected to couple processing requests to and receive processed data from, selected children, the children of the request distribution nodes of the leaf level comprising the processing nodes. Each request distribution node, in response to request address information received from its parent, identifies selected ones of its children and thereafter couples further request address information which it receives and processing requests in parallel to its children.

摘要翻译： 一种包括多个处理节点，控制节点和请求分发网络的计算机。 每个处理节点接收处理请求并响应处理的数据生成。 控制节点生成用于传送到由相关联的请求地址信息识别的所选处理节点的处理请求，并响应于接收处理的数据，请求地址信息识别处理节点中选择的一个并行接收处理请求。 请求分配网络将处理请求分配给处理节点，并将处理后的数据返回给控制节点。 网络包括以多个级别连接的多个请求分发节点，以形成包括上根级和下叶级的树结构。 每个请求分发节点被连接以接收处理的请求，并且将处理的数据耦合到父节点，包括控制节点的根级别的请求分发节点的父节点，并且每个请求分配节点进一步连接以耦合处理请求 从所选择的孩子接收和接收包括处理节点的叶级别的请求分发节点的子节点。 每个请求分发节点响应于从其父节点接收到的请求地址信息，识别其子节点中的所选择的一个，然后将其接收到的进一步的请求地址信息与其子节点并行处理请求。

公开(公告)号：US06883162B2

公开(公告)日：2005-04-19

申请号：US09876269

申请日：2001-06-06

申请人： Christopher J. Jackson ,  Robert C. Zak, Jr.

发明人： Christopher J. Jackson ,  Robert C. Zak, Jr.

IPC分类号： G06F11/34 ,  G06F9/44

CPC分类号： G06F11/3466

摘要： A method and mechanism for annotating a transaction stream. A processing unit is configured to generate annotation transactions which are inserted into a transaction stream. The transaction stream, including the annotations, are subsequently observed by a trace unit for debug or other analysis. In one embodiment, a processing unit includes a trace address register and an annotation enable bit. The trace address register is configured to store an address corresponding to a trace unit and the enable bit is configured to indicate whether annotation transactions are to be generated. Annotation instructions are added to operating system or user code at locations where annotations are desired. In one embodiment, annotation transactions correspond to transaction types which are not unique to annotation transactions. In one embodiment, an annotation instruction includes a reference to the trace address register which contains the address of the trace unit. Upon detecting the annotation instruction, and detecting annotations are enabled, the processing unit generates an annotation transaction addressed to the trace unit. In one embodiment, annotation transactions may be used to indicate context switches, processor mode changes, timestamps, or address translation information.

摘要翻译： 一种用于注释事务流的方法和机制。 处理单元被配置为生成插入到事务流中的注释事务。 事务流（包括注释）随后由跟踪单元用于调试或其他分析。 在一个实施例中，处理单元包括跟踪地址寄存器和注释使能位。 跟踪地址寄存器被配置为存储与跟踪单元相对应的地址，并且使能位被配置为指示是否要生成注释事务。 注释说明在需要注释的位置添加到操作系统或用户代码。 在一个实施例中，注释事务对应于不是注释事务唯一的事务类型。 在一个实施例中，注释指令包括对包含跟踪单元的地址的跟踪地址寄存器的引用。 在检测到注释指令并且启用检测注释时，处理单元生成寻址到跟踪单元的注释事务。 在一个实施例中，注释事务可以用于指示上下文切换，处理器模式改变，时间戳或地址转换信息。