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    Insulated gate power semiconductor devices
    1.
    发明申请
    Insulated gate power semiconductor devices 失效
    绝缘栅功率半导体器件

    公开(公告)号：US20060189063A1

    公开(公告)日：2006-08-24

    申请号：US10564214

    申请日：2003-07-12

    申请人： Raymond Hueting ,  Erwin Hijzen ,  Michael In't Zandt

    发明人： Raymond Hueting ,  Erwin Hijzen ,  Michael In't Zandt

    IPC分类号： H01L21/8238 ,  H01L29/76

    CPC分类号： H01L29/7813 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238

    摘要： A trench-gate semiconductor device (100) has a trench network (STR1), ITR1) surrounding a plurality of closed transistor cells (TCS). The trench network comprises segment trench regions (STR1) adjacent sides of the transistor cells (TCS) and intersection trench regions (ITR1) adjacent corners of the transistor cells. As shown in FIG. 16 which is a section view along the line II-II of FIG. 11, the intersection trench regions (ITR1) each include insulating material (21D) which extends from the bottom of the intersection trench region with a thickness which is greater than the thickness of the insulating material (21B1) at the bottom of the segment trench regions (STR1). The greater thickness of the insulating material (21D) extending from the bottom of the intersection trench regions (ITR1) is effective to increase the drain-source reverse breakdown voltage of the device (100). The insulating material (21D) which extends from the bottom of each intersection trench region (ITR1) may extend upwards to thicken the insulating material at the corners of the cells (TCS) over at least part of the vertical extent of the channel-accommodating body region (23) so as to increase the threshold voltage of the device.

    摘要翻译： 沟槽栅极半导体器件（100）具有围绕多个闭合晶体管单元（TCS）的沟槽网络（STR1），ITR 1）。 沟槽网络包括晶体管单元（TCS）的相邻侧的分段沟槽区域（STR 1）和晶体管单元的相邻角的交叉沟槽区域（ITR 1）。 如图所示。 图16是沿图1的II-II线的剖视图。 如图11所示，交点沟槽区域（ITR 1）各自包括从交叉沟槽区域的底部延伸的绝缘材料（21D），其厚度大于绝缘材料（21B 1）的底部的厚度 段沟槽区域（STR 1）。 从交叉沟槽区域（ITR 1）的底部延伸的绝缘材料（21D）的较大厚度对于增加器件（100）的漏 - 源反向击穿电压是有效的。 从每个交叉沟槽区域（ITR 1）的底部延伸的绝缘材料（21D）可以向上延伸，以在通道的垂直方向的至少一部分的至少部分的细胞（TCS）上增厚绝缘材料， 容纳体区域（23），以增加装置的阈值电压。

    Edge termination in MOS transistors
    2.
    发明申请
    Edge termination in MOS transistors 失效

    公开(公告)号：US20050156232A1

    公开(公告)日：2005-07-21

    申请号：US11066408

    申请日：2005-02-25

    申请人： Raymond Hueting ,  Erwin Hijzen ,  Michael In't Zandt

    发明人： Raymond Hueting ,  Erwin Hijzen ,  Michael In't Zandt

    IPC分类号： H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78 ,  H01L29/76 ,  H01L21/336

    CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/7397 ,  H01L29/7811

    摘要： A RESURF trench gate MOSFET has a sufficiently small pitch (close spacing of neighbouring trenches) that intermediate areas of the drain drift region are depleted in the blocking condition of the MOSFET. However, premature breakdown can still occur in this known device structure at the perimeter/edge of the active device area and/or adjacent the gate bondpad. To counter premature breakdown, the invention adopts two principles: the gate bondpad is either connected to an underlying stripe trench network surrounded by active cells, or is directly on top of the active cells, and a compatible 2D edge termination scheme is provided around the RESURF active device area. These principles can be implemented in various cellular layouts e.g. a concentric annular device geometry, which may be circular or rectangular or ellipsoidal, in the active area and in the edge termination, or a device array of such concentric hexagonal or circular stripe cells, or a device array of square active cells with stripe edge cells, or a device array of hexagonal active cells with an edge termination of hexagonal edge cells.

    Manufacture of trench-gate semiconductor devices
    5.
    发明申请
    Manufacture of trench-gate semiconductor devices 有权
    沟槽栅半导体器件的制造

    公开(公告)号：US20060205222A1

    公开(公告)日：2006-09-14

    申请号：US10538214

    申请日：2003-12-08

    申请人： Michael In't Zandt ,  Erwin Hijzen

    发明人： Michael In't Zandt ,  Erwin Hijzen

    IPC分类号： H01L21/8242 ,  H01L21/311

    CPC分类号： H01L29/7813 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518

    摘要： A method of manufacturing a trench-gate semiconductor device (1), the method including forming trenches (20) in a semiconductor body (10) in an active transistor cell area of the device, the trenches (20) each having a trench bottom and trench sidewalls, and providing silicon oxide gate insulation (21) in the trenches such that the gate insulation (33) at the trench bottoms is thicker than the gate insulation (21) at the trench sidewalls in order to reduce the gate-drain capacitance of the device. The method includes, after forming the trenches (20), the steps of: (a) forming a silicon oxide layer (21) at the trench bottoms and trench sidewalls; (b) depositing a layer of doped polysilicon (31) adjacent the trench bottoms and trench side walls; (c) forming silicon nitride spacers (32) on the doped polysilicon (21) adjacent the trench sidewalls leaving the doped polysilicon exposed at the trench bottoms; (d) thermally oxidising the exposed doped polysilicon to grow said thicker gate insulation (33) at the trench bottoms; (e) removing the silicon nitride spacers (32); and (f) depositing gate conductive material (34) within the trenches to form a gate electrode for the device. The final thickness of the thicker gate insulation (33) at the trench bottoms is well controlled by the thickness of the layer of doped polysilicon (31) deposited in step (b). Also the doped (preferably greater than 5 e 19 cm-3) polysilicon oxidises fast at low temperatures (preferably 700-800° C.), reducing the risk of diffusing (e.g. p body) implantations present in the device at that stage.

    摘要翻译： 一种制造沟槽栅极半导体器件（1）的方法，所述方法包括在器件的有源晶体管单元区域中的半导体本体（10）中形成沟槽（20），所述沟槽（20）各自具有沟槽底部和 沟槽侧壁，并且在沟槽中提供氧化硅栅极绝缘体（21），使得在沟槽底部处的栅极绝缘体（33）比沟槽侧壁处的栅极绝缘体（21）更厚，以便降低栅极 - 漏极电容 装置。 该方法包括在形成沟槽（20）之后的步骤：（a）在沟槽底部和沟槽侧壁处形成氧化硅层（21）; （b）在沟槽底部和沟槽侧壁附近沉积一层掺杂多晶硅（31）; （c）在与沟槽侧壁相邻的掺杂多晶硅（21）上形成氮化硅间隔物（32），留下在沟槽底部暴露的掺杂多晶硅; （d）热氧化暴露的掺杂多晶硅以在沟槽底部生长所述较厚的栅极绝缘体（33）; （e）去除氮化硅间隔物（32）; 和（f）在所述沟槽内淀积栅极导电材料（34）以形成所述器件的栅电极。 沟槽底部较厚的栅极绝缘体（33）的最终厚度由步骤（b）中沉积的掺杂多晶硅层（31）的厚度很好地控制。 此外，掺杂（优选大于5埃19厘米3）的多晶硅在低温（优选700-800℃）下快速氧化，降低了在该阶段存在于器件中的扩散（例如p体）植入的风险。