公开(公告)号：US10304511B1

公开(公告)日：2019-05-28

申请号：US15959669

申请日：2018-04-23

Applicant: Everspin Technologies Inc.

Inventor： Syed M. Alam ,  Yaojun Zhang ,  Thomas Andre

IPC: G11C11/16 ,  H03K5/1534 ,  H03K5/00

Abstract: The present disclosure is drawn to, among other things, a magnetoresistive memory. The magnetoresistive memory comprises a first memory cell, a first clock-generating circuit, and a second clock-generating circuit. The first clock-generating circuit is configured to provide a first output signal and a second output signal. The second clock-generating circuit is configured to provide a third output signal and a fourth output signal. The first output signal, the second output signal, the third output signal, and the fourth output signal are configured for controlling access operations for the first memory cell.

公开(公告)号：US12165684B2

公开(公告)日：2024-12-10

申请号：US18297793

申请日：2023-04-10

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Yaojun Zhang ,  Frederick Neumeyer

IPC: G11C11/16

Abstract: The present disclosure is drawn to a magnetoresistive device including an array of memory cells arranged in rows and columns, each memory cell comprising a magnetic tunnel junction, each row comprising a word line, and each column comprising a bit line; a column select device that selects a bit line. The magnetoresistive device also includes a sense amplifier comprising a first input corresponding to a selected bit line, a second input corresponding to a reference bit line, and a data output. The plurality of columns comprise a reference column, the reference column comprising a conductive element coupled to the magnetic tunnel junctions in the reference column.

公开(公告)号：US20180322918A1

公开(公告)日：2018-11-08

申请号：US15840214

申请日：2017-12-13

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Yaojun Zhang

IPC: G11C11/56 ,  H01L43/12 ,  H01L43/08 ,  H01L43/02 ,  G11C11/16 ,  H01L27/11 ,  G11C11/419

CPC classification number: G11C11/5607 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1675 ,  G11C11/1693 ,  G11C11/419 ,  G11C2013/0071 ,  H01L27/11 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: Higher word line voltages facilitate write operations in spin-torque magnetic memory devices, but overdriving the gate of a selection transistor with such higher word line voltages can damage the selection transistor if the gate-to-source voltage for the selection transistor is too high. Therefore in order to support the word line voltage needed on the gate of the select transistor for an up-current write operation without exceeding limits on the gate-to-source voltage for the select transistor, the gate of the selection transistor can be driven in a two-step process. The gate of the selection transistor is first driven to a lower voltage within the limits of the gate-to-source voltage for the transistor when the source of the transistor is grounded or at a voltage near ground. A voltage is then applied across the memory cell, which results in the source of the selection transistor being raised above its initial ground or near-ground state. After the source of the selection transistor has been raised, the gate voltage of the selection transistor can also be raised at least as much as the source of the selection transistor has been elevated without violating the limits on the gate-to-source voltage for the selection transistor.

公开(公告)号：US11651807B2

公开(公告)日：2023-05-16

申请号：US17113595

申请日：2020-12-07

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Yaojun Zhang ,  Frederick Neumeyer

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/1659 ,  G11C11/1657

Abstract: The present disclosure is drawn to a magnetoresistive device including an array of memory cells arranged in rows and columns, each memory cell comprising a magnetic tunnel junction, each row comprising a word line, and each column comprising a bit line; a column select device that selects a bit line. The magnetoresistive device also includes a sense amplifier comprising a first input corresponding to a selected bit line, a second input corresponding to a reference bit line, and a data output. The plurality of columns comprise a reference column, the reference column comprising a conductive element coupled to the magnetic tunnel junctions in the reference column.

公开(公告)号：US10446213B1

公开(公告)日：2019-10-15

申请号：US15980977

申请日：2018-05-16

Applicant: Everspin Technologies Inc.

Inventor： Yaojun Zhang ,  Syed M. Alam ,  Thomas Andre

IPC: G11C11/00 ,  G11C11/16

Abstract: The present disclosure is drawn to, among other things, a magnetoresistive memory. The magnetoresistive memory includes a first memory cell, a first access circuit, a second access circuit, and a current generating circuit. The first memory cell includes a first magnetic tunnel junction and a second magnetic tunnel junction. The first access circuit is configured to receive access command signals for accessing the first magnetic tunnel junction. The first access circuit includes a first access switch and a second access switch. The second access circuit is configured to receive access command signals for accessing the second magnetic tunnel junction. The second access circuit includes a third access switch and a fourth access switch. The current generating circuit is configured to generate a first write current through the first magnetic tunnel junction and generate a second write current through the second magnetic tunnel junction based on data input signals.

公开(公告)号：US10249364B2

公开(公告)日：2019-04-02

申请号：US15840214

申请日：2017-12-13

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Yaojun Zhang

IPC: G11C11/56 ,  G11C11/16 ,  H01L43/12 ,  G11C11/419 ,  H01L27/11 ,  H01L43/02 ,  H01L43/08 ,  G11C13/00

Abstract: Higher word line voltages facilitate write operations in spin-torque magnetic memory devices, but overdriving the gate of a selection transistor with such higher word line voltages can damage the selection transistor if the gate-to-source voltage for the selection transistor is too high. Therefore in order to support the word line voltage needed on the gate of the select transistor for an up-current write operation without exceeding limits on the gate-to-source voltage for the select transistor, the gate of the selection transistor can be driven in a two-step process. The gate of the selection transistor is first driven to a lower voltage within the limits of the gate-to-source voltage for the transistor when the source of the transistor is grounded or at a voltage near ground. A voltage is then applied across the memory cell, which results in the source of the selection transistor being raised above its initial ground or near-ground state. After the source of the selection transistor has been raised, the gate voltage of the selection transistor can also be raised at least as much as the source of the selection transistor has been elevated without violating the limits on the gate-to-source voltage for the selection transistor.

公开(公告)号：US09997239B1

公开(公告)日：2018-06-12

申请号：US15584232

申请日：2017-05-02

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： Syed M. Alam ,  Yaojun Zhang

IPC: G11C11/16 ,  G11C11/56 ,  G11C11/419 ,  H01L27/11 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

CPC classification number: H01L43/12 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1675 ,  G11C11/1693 ,  G11C2013/0071 ,  H01L27/11

Abstract: Higher word line voltages facilitate write operations in spin-torque magnetic memory devices, but overdriving the gate of a selection transistor with such higher word line voltages can damage the selection transistor if the gate-to-source voltage for the selection transistor is too high. Therefore in order to support the word line voltage needed on the gate of the select transistor for an up-current write operation without exceeding limits on the gate-to-source voltage for the select transistor, the gate of the selection transistor can be driven in a two-step process. The gate of the selection transistor is first driven to a lower voltage within the limits of the gate-to-source voltage for the transistor when the source of the transistor is grounded or at a voltage near ground. A voltage is then applied across the memory cell, which results in the source of the selection transistor being raised above its initial ground or near-ground state. After the source of the selection transistor has been raised, the gate voltage of the selection transistor can also be raised at least as much as the source of the selection transistor has been elevated without violating the limits on the gate-to-source voltage for the selection transistor.