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公开(公告)号：US08160091B2
公开(公告)日：2012-04-17
申请号：US11817791
申请日：2006-03-01
IPC分类号： H04L12/43
CPC分类号： H04J3/0635 , H04L7/0008
摘要： A data processing system according to the invention comprising a group of at least a first and a second module, wherein each module has a data processing facility, a clock for timing data transmissions from the module to another module, a time-slot counter for counting a number of time slots which are available for transmission of data. The modules have a first operational state wherein the counted number of time slots is less than or equal to a predetermined number, in which operational state data transmission is enabled, and a second operational state wherein the number is in excess of the predetermined number, in which second operational state data transmission is disabled, Each module has a notifying facility for notifying when it is in the second operational state. The data processing system has at least one detecting facility that detects whether the other modules have notified that they are in the second operational state and the modules each have an initialization facility for resetting the time-slot counter when the module is in the second operational state and each of the other modules has notified that it is in the second operational state.
摘要翻译： 根据本发明的数据处理系统包括至少第一和第二模块的组，其中每个模块具有数据处理设施，用于从模块到另一模块的定时数据传输的时钟，用于计数的时隙计数器 可用于传输数据的多个时隙。 模块具有第一操作状态，其中计数的时隙数小于或等于预定数量，其中操作状态数据传输被使能，以及第二操作状态，其中该数量超过预定数量，在 哪个第二操作状态数据传输被禁用，每个模块具有通知设备，用于在何时处于第二操作状态。 数据处理系统具有至少一个检测装置，其检测其他模块是否已经通知它们处于第二操作状态，并且模块各自具有用于当模块处于第二操作状态时复位时隙计数器的初始化设施 并且每个其他模块已经通知它处于第二操作状态。
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公开(公告)号：US20090172198A1
公开(公告)日：2009-07-02
申请号：US11817791
申请日：2006-03-01
IPC分类号： G06F15/16
CPC分类号： H04J3/0635 , H04L7/0008
摘要： A data processing system according to the invention comprising a group of at least a first and a second module, wherein each module has a data processing facility, a clock for timing data transmissions from the module to another module, a time-slot counter for counting a number of time slots which are available for transmission of data. The modules have a first operational state wherein the counted number of time slots is less than or equal to a predetermined number, in which operational state data transmission is enabled, and a second operational state wherein the number is in excess of the predetermined number, in which second operational state data transmission is disabled, Each module has a notifying facility for notifying when it is in the second operational state. The data processing system has at least one detecting facility that detects whether the other modules have notified that they are in the second operational state and the modules each have an initialization facility for resetting the time-slot counter when the module is in the second operational state and each of the other modules has notified that it is in the second operational state.
摘要翻译： 根据本发明的数据处理系统包括至少第一和第二模块的组，其中每个模块具有数据处理设施，用于从模块到另一模块的定时数据传输的时钟，用于计数的时隙计数器 可用于传输数据的多个时隙。 模块具有第一操作状态，其中计数的时隙数小于或等于预定数量，其中操作状态数据传输被使能，以及第二操作状态，其中该数量超过预定数量，在 哪个第二操作状态数据传输被禁用，每个模块具有通知设备，用于在何时处于第二操作状态。 数据处理系统具有至少一个检测装置，其检测其他模块是否已经通知它们处于第二操作状态，并且模块各自具有用于当模块处于第二操作状态时复位时隙计数器的初始化设施 并且每个其他模块已经通知它处于第二操作状态。
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公开(公告)号：US20080259699A1
公开(公告)日：2008-10-23
申请号：US11575865
申请日：2005-09-19
CPC分类号： G11C5/14
摘要： The present invention relates to a memory circuit and a method of controlling data retention in the memory circuit, wherein a supply signal is selectively switched to a respective one of at least two virtual supply lines (24) each shared by a respective one of a plurality of groups (30-1 to 30-n) of memory cells (C0,0 to Cy,z). The selective switching is controlled based on a global activity control signal (A), used for setting the memory circuit either into a standby state or into an active state, and a local data retention indication signal (DR1 to DRn) allocated to a dedicated group of memory cells. Thereby, the data retention part of the memory circuit can be adapted to the application and its state, and standby mode leakaged power is only dissipated in those memory cells for which data retentions actually required.
摘要翻译： 本发明涉及一种存储电路和一种控制存储电路中的数据保持的方法，其中电源信号选择性地切换到由多个相应的一个共享的至少两个虚拟电源线（24）中的相应一个 的组（30-1至30-n）的存储器单元（C 0,0至C y，z）。 基于用于将存储电路设置为待机状态或活动状态的全局活动控制信号（A）和分配给专用的本地数据保持指示信号（DR 1至DRn）来控制选择性切换 一组记忆细胞。 因此，存储器电路的数据保持部分可以适用于应用及其状态，并且待机模式泄漏功率仅在实际需要数据保持的那些存储单元中消散。
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公开(公告)号：US20080151692A1
公开(公告)日：2008-06-26
申请号：US11572599
申请日：2005-07-20
IPC分类号： G01S15/74
CPC分类号： G01S15/74
摘要： A location system including a base station (120, 200) and a responder tag (140, 250) that communicate using an acoustic signal to determine the location of the tag in a bounded 3D space (100). The base station transmits a request signal (310) encoded with the identifier of a particular tag. The particular tag responds after a fixed delay (t2−t1) with an acoustic response signal (330). The base station determines the location of the tag based on the received line of sight signal (330) and its reflections (340). The response signal may be encoded with data indicating a status of the tag, or data from associated sensors (270) or actuators (280). The request signal may also be encoded with data for controlling the tag or the associated sensors and actuators. A power management scheme may be carried out by the tag.
摘要翻译： 一种位置系统，包括使用声信号进行通信的基站（120,200）和应答器标签（140,250），以确定所述标签在有界3D空间（100）中的位置。 基站发送用特定标签的标识符编码的请求信号（310）。 特定标签在具有声响应信号（330）的固定延迟（t 2 -t 1）之后进行响应。 基站基于接收到的视线信号（330）及其反射（340）来确定标签的位置。 响应信号可以用指示标签的状态的数据或来自相关传感器（270）或致动器（280）的数据进行编码。 请求信号也可以用用于控制标签或相关联的传感器和致动器的数据进行编码。 电源管理方案可以由标签执行。
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公开(公告)号：US07259594B2
公开(公告)日：2007-08-21
申请号：US10571953
申请日：2004-08-30
申请人： Adrianus Marinus Gerardus Peeters , Cornelis Hermanus Van Berkel , Mark Nadim Olivier De Clercq
发明人： Adrianus Marinus Gerardus Peeters , Cornelis Hermanus Van Berkel , Mark Nadim Olivier De Clercq
IPC分类号： H03K19/00
CPC分类号： G06F15/8053 , G06F1/32
摘要： A chain of processing element (10a, 10, 10b) with a logic circuit (14) and a storage element (12) is provided. The storage elements (12) of all except a final processing element (10b) in the chain have one or more outputs coupled to the logic (14) of a next processing element (10a, 10, 10b) in the chain. A timing circuit (16) controls respective loading time points at which the storage elements (12) load data from the logic circuits (14) in respective ones of the processing elements (10a, 10, 10b). The data is loaded progressively later in processing elements (10a, 10, 10b) that successively precede one another in the chain. The time interval between successive loading time points of the final processing element (10b) includes loading time points of loading all processing elements (10a, 10) other than the final processing element (10).
摘要翻译： 提供具有逻辑电路（14）和存储元件（12）的处理元件链（10a，10,10b）链。 链中的最终处理元件（10b）之外的所有存储元件（12）具有耦合到链中的下一个处理元件（10a，10,10b）的逻辑（14）的一个或多个输出。 定时电路（16）控制存储元件（12）在各个处理元件（10a，10,10b）中从逻辑电路（14）加载数据的各个加载时间点。 稍后在链中相继前进的处理元件（10a，10,10b）中逐渐加载数据。 最终处理元件（10b）的连续加载时间点之间的时间间隔包括加载除了最终处理元件（10）之外的所有处理元件（10a，10）的加载时间点。
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公开(公告)号：US07804732B2
公开(公告)日：2010-09-28
申请号：US11575865
申请日：2005-09-19
IPC分类号： G11C5/14
CPC分类号： G11C5/14
摘要： The present invention relates to a memory circuit and a method of controlling data retention in the memory circuit, wherein a supply signal is selectively switched to a respective one of at least two virtual supply lines (24) each shared by a respective one of a plurality of groups (30-1 to 30-n) of memory cells (C0,0 to Cy,z). The selective switching is controlled based on a global activity control signal (A), used for setting the memory circuit either into a standby state or into an active state, and a local data retention indication signal (DR1 to DRn) allocated to a dedicated group of memory cells. Thereby, the data retention part of the memory circuit can be adapted to the application and its state, and standby mode leakaged power is only dissipated in those memory cells for which data retentions actually required.
摘要翻译： 本发明涉及一种存储电路和一种控制存储电路中的数据保持的方法，其中电源信号选择性地切换到由多个相应的一个共享的至少两个虚拟电源线（24）中的相应一个 的存储单元（C0,0至Cy，z）的组（30-1至30-n）。 基于用于将存储电路设置为待机状态或活动状态的全局活动控制信号（A）以及分配给专用组的本地数据保持指示信号（DR1至DRn）来控制选择性切换 的记忆细胞。 因此，存储器电路的数据保持部分可以适用于应用及其状态，并且待机模式泄漏功率仅在实际需要数据保持的那些存储单元中消散。
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公开(公告)号：US07684832B2
公开(公告)日：2010-03-23
申请号：US10515081
申请日：2003-05-19
IPC分类号： H04B1/38
CPC分类号： H04W48/16 , H04W52/0216 , H04W52/0229 , Y02D70/1222 , Y02D70/1242 , Y02D70/164
摘要： To achieve a shortening of the initial synchronization time and/or extension of the stand-by time with a method of connecting an UMTS mobile radio to a network, the UMTS mobile radio receives and stored in one or more time-limited RF receive windows the signals that are subsequently evaluated when the HF receiver is switched off.
摘要翻译： 为了通过将UMTS移动无线电连接到网络的方法来实现初始同步时间的缩短和/或待机时间的扩展，UMTS移动无线电接收并存储在一个或多个有时限的RF接收窗口中 随后在HF接收机关闭时进行评估的信号。
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公开(公告)号：US20080059551A1
公开(公告)日：2008-03-06
申请号：US10565926
申请日：2004-07-13
IPC分类号： G06F7/38
CPC分类号： H04J13/105
摘要： Configurable vector processors can be equipped with code generators, so that they are capable of handling different standards and codes. Furthermore, they can be arranged to provide support for related functions such as cyclic redundancy check (CRC). A configurable vector processor would then be equipped with a plurality of generators which generate basic codes in vector format. However, a disadvantage of such a configurable vector processor is that it cannot provide a composite code which is dependent on such basic codes. This is necessary if the configurable vector processors should be flexible enough to support a variety of CDMA-like standards. The device according to the invention is provided with at least two weighted sum units, which are able to make a selection out of a plurality of incoming basic-code vectors by means of a weighted sum operation, under the control of a configuration word. The elements of this configuration word represent the weighting factors which are used to select or deselect a basic-code vector. The selected basic-code vectors are added together and the result of the weighted sum operation is then output as an intermediate-code vector. Subsequently, the intermediate-code vectors are added together by an add unit and output as a composite-code vector. The ability to make selections out of a plurality of incoming basic-code vectors and to add intermediate-code vectors into a composite-code vector, together with the ability to configure the operations of the functional units of the device by means of configuration words, increases the flexibility of the device significantly. This flexibility is needed to support a variety of transmission standards.
摘要翻译： 可配置向量处理器可以配备代码生成器，以便它们能够处理不同的标准和代码。 此外，它们可以被布置成为诸如循环冗余校验（CRC）之类的相关功能提供支持。 然后，可配置的向量处理器将配备有以矢量格式生成基本代码的多个生成器。 然而，这种可配置向量处理器的缺点在于它不能提供依赖于这种基本代码的复合代码。 如果可配置矢量处理器应足够灵活以支持各种类似CDMA的标准，则这是必要的。 根据本发明的装置具有至少两个加权和单元，它们能够在配置字的控制下通过加权和运算从多个输入的基本码矢量中进行选择。 该配置字的元素表示用于选择或取消选择基本码矢量的加权因子。 所选择的基本码矢量相加在一起，然后将加权和运算的结果作为中间码矢量输出。 随后，通过加法单元将中间码矢量相加在一起，作为复合码矢量输出。 从多个输入的基本代码向量中进行选择并将中间代码向量添加到复合代码向量中的能力以及通过配置字配置设备的功能单元的操作的能力， 显着增加了设备的灵活性。 需要这种灵活性来支持各种传输标准。
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公开(公告)号：US20110051501A1
公开(公告)日：2011-03-03
申请号：US12871834
申请日：2010-08-30
IPC分类号： G11C5/14 , G11C11/413 , G11C7/00
CPC分类号： G11C5/14
摘要： The present invention relates to a memory circuit and a method of controlling data retention in the memory circuit, wherein a supply signal is selectively switched to a respective one of at least two virtual supply lines (24) each shared by a respective one of a plurality of groups (30-1 to 30-n) of memory cells (C0,0 to Cy,z). The selective switching is controlled based on a global activity control signal (A), used for setting the memory circuit either into a standby state or into an active state, and a local data retention indication signal (DR1 to DRn) allocated to a dedicated group of memory cells. Thereby, the data retention part of the memory circuit can be adapted to the application and its state, and standby mode leakaged power is only dissipated in those memory cells for which data retentions actually required.
摘要翻译： 本发明涉及一种存储电路和一种控制存储电路中的数据保持的方法，其中电源信号选择性地切换到由多个相应的一个共享的至少两个虚拟电源线（24）中的相应一个 的存储单元（C0,0至Cy，z）的组（30-1至30-n）。 基于用于将存储电路设置为待机状态或活动状态的全局活动控制信号（A）以及分配给专用组的本地数据保持指示信号（DR1至DRn）来控制选择性切换 的记忆细胞。 因此，存储器电路的数据保持部分可以适用于应用及其状态，并且待机模式泄漏功率仅在实际需要数据保持的那些存储单元中消散。
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公开(公告)号：US07774573B2
公开(公告)日：2010-08-10
申请号：US10562887
申请日：2004-06-30
IPC分类号： G06F12/00
CPC分类号： G06F5/10
摘要： The present invention relates to a memory device comprising a memory (EM) having at least two predetermined register memory sections addressable by respective address ranges AS1-ASz) and at least one access port (P1-PZ) for providing access to said memory (EM). Furthermore, access control means (A) are provided for addressing said memory (EM) so as to operate said register memory sections as shift registers and to map shift register accesses of the at least one access port (P1 to PZ) to predetermined addresses in the global address space of the memory (EM). In this way, it is possible to combine a plurality of FIFO memories in a single addressable memory device. This implementation is favourable in view of power consumption and area. Furthermore, by introducing a buffer memory, a multi-port memory device can be replaced by a single-port memory device of the same capacity. This advanced implementation also provides a reduced cycle and access time.
摘要翻译： 本发明涉及一种包括具有至少两个可由各个地址范围AS1-ASz寻址的预定寄存器存储器区域的存储器（EM））和至少一个访问端口（P1-PZ）的存储设备，用于提供对所述存储器 ）。 此外，提供访问控制装置（A）用于寻址所述存储器（EM），以便将所述寄存器存储器部分作为移位寄存器操作，并将至少一个访问端口（P1至PZ）的移位寄存器访问映射到预定地址 存储器（EM）的全局地址空间。 以这种方式，可以在单个可寻址存储器件中组合多个FIFO存储器。 考虑到功耗和面积，这种实现是有利的。 此外，通过引入缓冲存储器，可以由相同容量的单端口存储器件替换多端口存储器件。 这种高级实现还提供了减少的周期和访问时间。
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