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公开(公告)号：US07259594B2
公开(公告)日：2007-08-21
申请号：US10571953
申请日：2004-08-30
申请人： Adrianus Marinus Gerardus Peeters , Cornelis Hermanus Van Berkel , Mark Nadim Olivier De Clercq
发明人： Adrianus Marinus Gerardus Peeters , Cornelis Hermanus Van Berkel , Mark Nadim Olivier De Clercq
IPC分类号： H03K19/00
CPC分类号： G06F15/8053 , G06F1/32
摘要： A chain of processing element (10a, 10, 10b) with a logic circuit (14) and a storage element (12) is provided. The storage elements (12) of all except a final processing element (10b) in the chain have one or more outputs coupled to the logic (14) of a next processing element (10a, 10, 10b) in the chain. A timing circuit (16) controls respective loading time points at which the storage elements (12) load data from the logic circuits (14) in respective ones of the processing elements (10a, 10, 10b). The data is loaded progressively later in processing elements (10a, 10, 10b) that successively precede one another in the chain. The time interval between successive loading time points of the final processing element (10b) includes loading time points of loading all processing elements (10a, 10) other than the final processing element (10).
摘要翻译： 提供具有逻辑电路（14）和存储元件（12）的处理元件链（10a，10,10b）链。 链中的最终处理元件（10b）之外的所有存储元件（12）具有耦合到链中的下一个处理元件（10a，10,10b）的逻辑（14）的一个或多个输出。 定时电路（16）控制存储元件（12）在各个处理元件（10a，10,10b）中从逻辑电路（14）加载数据的各个加载时间点。 稍后在链中相继前进的处理元件（10a，10,10b）中逐渐加载数据。 最终处理元件（10b）的连续加载时间点之间的时间间隔包括加载除了最终处理元件（10）之外的所有处理元件（10a，10）的加载时间点。
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公开(公告)号：US07308589B2
公开(公告)日：2007-12-11
申请号：US10578641
申请日：2004-11-03
IPC分类号： G06F1/00
CPC分类号： G06F1/3243 , G06F1/3203 , G06F1/3275 , G11C7/1006 , G11C7/1045 , G11C2207/104 , Y02D10/14 , Y02D10/152
摘要： An electronic circuit is provided that comprises a plurality of storage elements (101-105) arranged for storing of data elements, and a plurality of processing elements. The plurality of processing elements processes the data elements stored in the storage elements. In operation, the points in time at which respective storage elements load their data elements are mutually different in order to meet a maximum allowable value of the power consumption peaks.
摘要翻译： 提供了一种电子电路，其包括被布置用于存储数据元素的多个存储元件（101-105）和多个处理元件。 多个处理元件处理存储在存储元件中的数据元素。 在操作中，各个存储元件加载其数据元素的时间点是相互不同的，以便满足功耗峰值的最大允许值。
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公开(公告)号：US20080164929A1
公开(公告)日：2008-07-10
申请号：US11908966
申请日：2006-03-15
IPC分类号： H03H11/26
CPC分类号： H03K5/13 , G06F9/3869 , H03K2005/00058 , H03K2005/00247
摘要： The electronic circuit contains a basic delay circuit (14). A delay is realized by activating the same basic delay circuit (14) a plurality of times in response to a single start signal before generating a response to that start signal. A control circuit (12) receives a start signal and an outputs a response. The control circuit (12) causes a series of signals to be passed through the delay circuit (14), the series starting at a time that is time-continuously triggered by the start signal. Each successive signal in the series starts after a preceding signal has emerged from the delay circuit (12) and the series being terminated after a controlled number of more than one signal has been passed. The control circuit (12) supplies the response upon termination of the series. In one embodiment the series is realized by means of a handshake sequencing circuit (120) that generates a series of successive handshake transactions.
摘要翻译： 电子电路包含基本延迟电路（14）。 通过在产生对该起始信号的响应之前响应于单个起始信号激活相同的基本延迟电路（14）来实现延迟。 控制电路（12）接收起始信号并输出响应。 控制电路（12）使一系列信号通过延迟电路（14），该串联信号从由起始信号时间连续触发的时间开始。 在从延迟电路（12）出现先前的信号之后，串联中的每个连续信号开始，并且在经过多个信号的受控数量之后，串联被终止。 控制电路（12）在串联终止时提供响应。 在一个实施例中，该系列通过产生一系列连续握手事务的握手排序电路（120）来实现。
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公开(公告)号：US07185220B2
公开(公告)日：2007-02-27
申请号：US10500520
申请日：2002-12-06
CPC分类号： G06F1/08
摘要： A locally synchronous circuit module has a delay circuit having and input and output coupled to a clock input. The delay circuit provides a delay which when incorporated in a clock oscillator ensures a clock period that is at least as long as needed to transfer information between the storage elements. A handshake circuit is provided for generating handshake signals for timing information transfer between the locally synchronous circuit module and a further circuit. The handshake circuit comprises the delay circuit, so that at least part of the handshake signals during a handshake transaction are timed by traveling through the delay circuit and are applied to the clock input to clock the locally synchronous circuit module.
摘要翻译： 本地同步电路模块具有延迟电路，其具有耦合到时钟输入的输入和输出。 延迟电路提供了延迟，当并入时钟振荡器中时，可以确保在存储元件之间传送信息所需的时钟周期至少等同于长度。 提供握手电路，用于产生用于本地同步电路模块和另一电路之间的定时信息传送的握手信号。 握手电路包括延迟电路，使得在握手事务期间的握手信号的至少一部分通过行进延迟电路来计时，并被施加到时钟输入以对本地同步电路模块进行时钟。
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公开(公告)号：US06614290B2
公开(公告)日：2003-09-02
申请号：US10067044
申请日：2002-02-04
申请人： Patrick Willem Hubert Heuts , Jozef Laurentius Wilhelmus Kessels , Adrianus Marinus Gerardus Peeters
发明人： Patrick Willem Hubert Heuts , Jozef Laurentius Wilhelmus Kessels , Adrianus Marinus Gerardus Peeters
IPC分类号： G06F1100
CPC分类号： G01R31/318536
摘要： An integrated circuit according to the invention comprises at least a first and a second circuit (1, 2 resp.) and a first and a second signal path (10-20 and 11-21 resp.) between the first and the second circuit. The first and the second signal path each comprise a selection element (30) which has a first input (30a, 31a) coupled to the first circuit (1), and a second input (30b, 31b). The selection element (30) has an output (30c, 31c) coupled to the second circuit (2). The second input (31b) of the selection element (31) of the second signal path (11-21) is coupled to a memory element (41). The output (40a) of the selection element (30) of the first signal path (10-20) is coupled to an input (40a) of the memory element (40).
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公开(公告)号：US07519759B2
公开(公告)日：2009-04-14
申请号：US10542906
申请日：2004-01-14
CPC分类号： G06F9/3869 , H04L7/02
摘要： Pipeline synchronization device for transferring data between clocked devices having different clock frequencies. The Pipeline synchronization device comprises a mousetrap buffer for exchanging data with one of said external devices said mousetrap buffer having a signalling output for coordinating the data exchange with the external device. The pipeline synchronization device comprises further a synchronizer adapted to synchronizing the change in a signalling output with the clock of the external device.
摘要翻译： 用于在具有不同时钟频率的时钟设备之间传送数据的流水线同步装置。 管道同步装置包括用于与所述外部设备之一交换数据的捕鼠器缓冲器，所述捕鼠器缓冲器具有用于协调与外部设备的数据交换的信令输出。 流水线同步装置还包括一个同步器，该同步器适于使信令输出的变化与外部设备的时钟同步。
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公开(公告)号：US20130293783A1
公开(公告)日：2013-11-07
申请号：US13976483
申请日：2012-01-16
CPC分类号： H04N5/2625 , A63B24/0003 , A63B69/36 , A63B2220/806 , H04N5/145 , H04N5/44591 , H04N7/013 , H04N7/014
摘要： The present invention proposes to analyze movements of objects in video sequences (e.g. sport videos), by performing motion estimation to determine motion vectors at each frame. With the calculated motion vectors, the movements of the object(s) (e.g. athlete(s)) can be quantitatively measured. Based on this, movements in two videos can be compared at each individual frame of the video sequence. Different approaches (e.g., color coding) can be used to visualize and compare the movements. With motion estimation, intermediate frames can also be inserted to enable better movement comparison in two given videos.
摘要翻译： 本发明提出通过执行运动估计来确定每帧的运动矢量来分析视频序列（例如体育视频）中的对象的移动。 利用所计算的运动矢量，可以定量地测量物体（例如运动员）的运动。 基于此，可以在视频序列的每个单独的帧处比较两个视频中的移动。 可以使用不同的方法（例如，颜色编码）来可视化和比较运动。 通过运动估计，也可以插入中间帧，以便在两个给定的视频中实现更好的运动比较。
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公开(公告)号：US20080288837A1
公开(公告)日：2008-11-20
申请号：US11572930
申请日：2005-07-21
IPC分类号： G01R31/28
CPC分类号： G01R31/318533
摘要： Special test measures are required to test an asynchronous timing circuit. The asynchronous timing circuit (14) comprises a time-continuous feedback loop (22, 26) with a combinatorial logic circuit (22) with inputs for a feedback signal and a further signal, the feedback loop having positive loop gain. A test prepared circuit that contains the timing circuit is switched to a test mode. In the test mode test data through is shifted through a shift register structure (12). The further input signal of the feedback loop is controlled dependent on test data from the shift register structure (12). The time-continuous feedback loop (22, 26) is initially broken in the test mode, substituting test data from a register (31) in the shift register structure (12) for a feedback signal. Subsequently the time-continuous feedback loop is restored in the test mode after the further signal has stabilized. A test result that has been determined by the feedback loop is captured while the feedback loop is restored, for transport through the shift register structure (12). In this way no register needs to be added in the feedback loop for test purposes. As a result testability of the asynchronous timing circuit only imposes a minimum of delay.
摘要翻译： 测试异步定时电路需要特殊的测试措施。 异步定时电路（14）包括具有组合逻辑电路（22）的时间连续反馈回路（22,26），该组合逻辑电路具有用于反馈信号和另一信号的输入，所述反馈回路具有正回路增益。 包含定时电路的测试准备电路切换到测试模式。 在测试模式下，测试数据通过移位寄存器结构（12）。 反馈回路的另外的输入信号根据来自移位寄存器结构（12）的测试数据来进行控制。 时间连续反馈回路（22,26）在测试模式下被初始断开，代替来自移位寄存器结构（12）中的寄存器（31）的测试数据用于反馈信号。 随后在进一步的信号稳定后，在测试模式下恢复时间连续反馈回路。 当反馈回路恢复时，捕获由反馈回路确定的测试结果，以便通过移位寄存器结构（12）进行传输。 以这种方式，为了测试目的，无需在反馈回路中添加寄存器。 因此，异步定时电路的可测试性仅施加最小的延迟。
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9.发明授权Method and arrangement for increasing the security of circuits against unauthorized access 有权提高电路安全性以防止未经授权访问的方法和装置公开(公告)号：US07500110B2
公开(公告)日：2009-03-03
申请号：US10319894
申请日：2002-12-13
CPC分类号： H01L23/576 , G06K7/0086 , G06K7/0091 , G06K19/073 , H01L2924/0002 , H04L9/003 , H04L2209/08 , H01L2924/00
摘要： The invention relates to a method and an arrangement for increasing the security of circuits against unauthorized access, both of which can be used in particular to improve the security of cards, and particularly smart cards, against attacks in which the differential power analysis approach (DPA) is followed.DPA is a procedure that makes it possible to obtain not only purely functional details but also internal information stored in integrated circuits (e.g. smart-card controllers). The majority of non-clocked classes of circuit have the property that the performance of the circuit adjusts automatically to the voltage available.The invention adopts a new approach to enable integrated circuits and particularly non-clocked handshake logic to be protected against DPA. Advantage is taken in this case of a special property of self-timed logic by using a special power supply. As a result the processes in the self-timed logic take place in an unpredictable way and current consumption becomes affected by severe noise and DPA cannot be successfully applied.
摘要翻译： 本发明涉及一种用于增加针对未授权访问的电路的安全性的方法和装置，这两者可以特别用于提高卡的安全性，特别是针对其中差分功率分析方法（DPA）的攻击 ）。 DPA是一种使得不仅可以获得纯功能细节而且可以获得存储在集成电路（例如，智能卡控制器）中的内部信息的过程。 大多数非时钟级电路具有电路性能自动调整为可用电压的特性。 本发明采用新的方法来实现集成电路，特别是非时钟的握手逻辑以防止DPA。 在这种情况下，通过使用特殊电源，可以获得具有自定时逻辑特性的优点。 因此，自定时逻辑中的过程以不可预测的方式发生，电流消耗受到严重噪声的影响，DPA无法成功应用。
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公开(公告)号：US20090009210A1
公开(公告)日：2009-01-08
申请号：US11572998
申请日：2005-07-26
IPC分类号： H03K19/00
CPC分类号： G01R31/318586
摘要： Logic circuit comprising—at least a first combinational logic circuit 42—a first data latch 44 having a data input d and a data output q, said data output q being connected to an input of said first combinational logic circuit 42,—a second scannable data latch 43 having an output q connected to the data input d of said first data latch 44 and—a third scannable data latch 47 having an input d connected to an output of said first combinational logic circuit 42, wherein the second scannable data latch 43 is adapted to being driven by a first clock clk1, the first data latch 44 and the third scannable data latch 47 are adapted to being driven by a second clock clk2, the first and second clocks clk1 and clk2 being non-overlapping clock signals.
摘要翻译： 逻辑电路至少包括第一组合逻辑电路42-具有数据输入端d和数据输出端口q的第一数据锁存器44，所述数据输出端q连接到所述第一组合逻辑电路42的输入端， - 第二可扫描 数据锁存器43，其具有连接到所述第一数据锁存器44的数据输入端d的输出端q和具有连接到所述第一组合逻辑电路42的输出的输入端的第三可扫描数据锁存器47，其中第二可扫描数据锁存器43 适于由第一时钟clk1驱动，第一数据锁存器44和第三可扫描数据锁存器47适于由第二时钟clk2驱动，第一和第二时钟clk1和clk2是不重叠的时钟信号。
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