公开(公告)号：US20150256129A1

公开(公告)日：2015-09-10

申请号：US14571734

申请日：2014-12-16

Applicant: FUJITSU LIMITED

Inventor： MASARU SATO

IPC: H03F1/02 ,  H03F3/16

CPC classification number: H03F3/605 ,  H03F1/56 ,  H03F3/607 ,  H03F2200/222 ,  H03F2200/387 ,  H03F2200/451

Abstract: An amplifier circuit includes: plural transistors; plural first transmission lines respectively connected between input terminals of the plural transistors; plural second transmission lines respectively connected between output terminals of the plural transistors; an input node connected to the input terminal of a first stage transistor among the plural transistors; an output node connected to the output terminal of a final stage transistor among the plural transistors; and a capacitance connected to the output terminal of the first stage transistor via a third transmission line.

Abstract translation: 放大器电路包括：多个晶体管; 分别连接在多个晶体管的输入端之间的多个第一传输线; 分别连接在多个晶体管的输出端之间的多个第二传输线; 连接到所述多个晶体管中的第一级晶体管的输入端子的输入节点; 连接到所述多个晶体管中的最终级晶体管的输出端子的输出节点; 以及经由第三传输线连接到第一级晶体管的输出端子的电容。

公开(公告)号：US20150236657A1

公开(公告)日：2015-08-20

申请号：US14599639

申请日：2015-01-19

Applicant: FUJITSU LIMITED

Inventor： MASARU SATO

IPC: H03F1/34 ,  H03F3/16

CPC classification number: H03F3/601 ,  H03F1/342 ,  H03F1/56 ,  H03F2200/405 ,  H03F2200/72

Abstract: An amplifier circuit has a plurality of amplifiers configured to be connected in series, and each of the plurality of amplifiers has an amplifying element configured to non-inverting amplify a signal and a phase adjustment element configured to be connected to an output terminal of the amplifying element and to adjust a phase of the signal, wherein the amplifying element is subjected to negative feedback, and wherein a stability coefficient of a circuit in which the amplifying elements of the number the same as the number of the plurality of amplifiers are connected in series is less than 1.

Abstract translation: 放大器电路具有被配置为串联连接的多个放大器，并且多个放大器中的每个放大器具有被配置为同相放大信号的放大元件和被配置为连接到放大器的输出端子的相位调整元件 并且调整所述信号的相位，其中所述放大元件经受负反馈，并且其中与所述多个放大器的数量相同的数量的放大元件串联连接的电路的稳定系数 小于1。

公开(公告)号：US20150116036A1

公开(公告)日：2015-04-30

申请号：US14474640

申请日：2014-09-02

Applicant: FUJITSU LIMITED

Inventor： MASARU SATO

IPC: H03F3/193

CPC classification number: H03F3/193 ,  H03F3/607 ,  H03F2200/09

Abstract: An amplifier circuit includes: first and second nodes configured to receive input of differential signals; third and fourth nodes; a plurality of first inductors configured to be connected in series between the first and second nodes; a plurality of second inductors configured to be connected in series between the third and fourth nodes; a plurality of field effect transistors configured to have gates each configured to be connected between the plurality of first inductors, sources each configured to be connected to a reference potential node, and drains each configured to be connected between the plurality of second inductors; and a synthesizing unit configured to synthesize signals at the third and fourth nodes.

Abstract translation: 放大器电路包括：被配置为接收差分信号的输入的第一和第二节点; 第三和第四个节点; 多个第一电感器，被配置为串联连接在第一和第二节点之间; 多个第二电感器，被配置为串联连接在第三和第四节点之间; 多个场效应晶体管被配置为具有各自被配置为连接在所述多个第一电感器之间的栅极，各个被配置为连接到参考电位节点的源以及被配置为连接在所述多个第二电感器之间的各个漏极; 以及合成单元，被配置为在第三和第四节点处合成信号。

公开(公告)号：US20140368290A1

公开(公告)日：2014-12-18

申请号：US14273990

申请日：2014-05-09

Applicant: FUJITSU LIMITED

Inventor： MASARU SATO

IPC: H03H11/28

CPC classification number: H03H11/28 ,  H03F1/565 ,  H03H11/48

Abstract: A first transistor and a second transistor cascade-connected, a wiring which connects a drain of the first transistor and a gate of the second transistor, a capacitor whose one terminal is connected between the first transistor and the second transistor cascade-connected and whose other terminal is grounded, and a control circuit are included. The control circuit adjusts an inductance value by controlling a capacitance value of the capacitor or gate voltage of the first transistor or the second transistor.

Abstract translation: 连接第一晶体管的漏极和第二晶体管的栅极的第一晶体管和第二晶体管，一个端子连接在第一晶体管和第二晶体管级联连接的电容器，其另一个 端子接地，并且包括控制电路。 控制电路通过控制第一晶体管或第二晶体管的电容器的电容值或栅极电压来调整电感值。

公开(公告)号：US20170302235A1

公开(公告)日：2017-10-19

申请号：US15463452

申请日：2017-03-20

Applicant: FUJITSU LIMITED

Inventor： MASARU SATO

IPC: H03F3/193 ,  H03F1/56

CPC classification number: H03F3/193 ,  H03F1/523 ,  H03F1/56 ,  H03F1/565 ,  H03F2200/18 ,  H03F2200/222 ,  H03F2200/294 ,  H03F2200/387 ,  H03F2200/465 ,  H03F2200/72

Abstract: An amplification circuit has a field effect transistor, an input side matching circuit, an output side matching circuit, a capacitor, and a resistor. The input side matching circuit is connected between an input port and the source terminal of the field effect transistor and outputs an input signal that changes with a bias voltage as a center value. The output side matching circuit is connected between an output port and the drain terminal of the field effect transistor. The capacitor is connected between the gate terminal of the field effect transistor and a first reference voltage source. The resistor is connected between the gate terminal of the field effect transistor and the first reference voltage source.

公开(公告)号：US20170222004A1

公开(公告)日：2017-08-03

申请号：US15386025

申请日：2016-12-21

Applicant: FUJITSU LIMITED

Inventor： MASARU SATO

IPC: H01L29/423 ,  H01L29/778 ,  H01L29/417 ,  H01L23/66 ,  H03F3/24 ,  H01L23/482 ,  H01L27/06 ,  H03F1/02 ,  H03F3/193 ,  H01L29/20 ,  H01L23/64

CPC classification number: H01L29/42316 ,  H01L23/4821 ,  H01L23/645 ,  H01L23/66 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/778 ,  H01L29/7787 ,  H01L2223/6611 ,  H01L2223/6655 ,  H03F1/0205 ,  H03F3/14 ,  H03F3/193 ,  H03F3/195 ,  H03F3/245 ,  H03F2200/108 ,  H03F2200/451

Abstract: An amplifier has a plurality of gate finger electrodes, two gate connection electrodes, a plurality of source electrodes and a plurality of drain electrodes, and a plurality of drain connection elements. The plurality of gate finger electrodes are arranged pectinate on the surface of the active region of the semiconductor substrate. The two gate connection electrodes connect in common each of both ends of the plurality of gate finger electrodes. The plurality of source electrodes and the plurality of drain electrodes are arranged alternately on the surface of the semiconductor substrate between the plurality of gate finger electrodes. The plurality of drain connection elements connects in sequence the plurality of drain electrodes. The ratio of the inductance value of each drain connection element to the parasitic capacitance of the drain-source electrodes between the corresponding drain electrode and the source electrode is constant.

公开(公告)号：US20140247083A1

公开(公告)日：2014-09-04

申请号：US14164390

申请日：2014-01-27

Applicant: FUJITSU LIMITED

Inventor： MASARU SATO

IPC: H03D7/14

CPC classification number: H03D1/10 ,  H03D7/02 ,  H03D7/165 ,  H03G3/3052

Abstract: A receiving device includes a dividing circuit, N pieces of internal circuits, and an averaging circuit. The dividing circuit is configured to divide an input signal into N pieces of divided signals (where N is an integer of two or larger), and the N pieces of internal circuits are configured to receive and process the N pieces of divided signals. The averaging circuit is configured to receive N pieces of output signals from the N pieces of internal circuits, averaging the output signals, and output an averaged signal.

Abstract translation: 接收装置包括分频电路，N个内部电路和平均电路。 分频电路被配置为将输入信号划分为N个分割信号（其中N是2或更大的整数），并且N个内部电路被配置为接收和处理N个分割信号。 平均电路被配置为从N个内部电路接收N个输出信号，对输出信号进行平均，并输出平均的信号。

公开(公告)号：US20140152347A1

公开(公告)日：2014-06-05

申请号：US14029040

申请日：2013-09-17

Applicant: FUJITSU LIMITED

Inventor： MASARU SATO

IPC: H03B21/00

CPC classification number: H03B21/00 ,  H03H11/20

Abstract: A variable phase shifter. The variable phase shifter includes: a transmission line that outputs quadrature signals from a pair of output ports in response to an input signal of a specific frequency; a synthesizer that includes a first transistor connected to a first port of the pair of output ports and a second transistor connected to a second port of the pair of output ports, and that on input of the input signal takes signals output from the pair of output ports of the transmission line with a phase according to their respective load impedances and employs the first and the second transistors to amplify and combine the signals; and a phase controller that controls the phase of the output signal that is combined and output by the synthesizer by controlling the amplification operation of each of the first and second transistors of the synthesizer.

Abstract translation: 可变移相器。 可变移相器包括：响应于特定频率的输入信号从一对输出端口输出正交信号的传输线; 合成器，其包括连接到所述一对输出端口的第一端口的第一晶体管和连接到所述一对输出端口的第二端口的第二晶体管，并且在所述输入信号的输入端从所述一对输出端输出的信号 传输线的端口根据其相应的负载阻抗具有相位，并且采用第一和第二晶体管来放大和组合信号; 以及相位控制器，其通过控制合成器的第一和第二晶体管的放大操作来控制由合成器组合和输出的输出信号的相位。