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1.发明授权公开(公告)号：US07154793B2
公开(公告)日：2006-12-26
申请号：US10948562
申请日：2004-09-24
IPC分类号： G11C29/06
CPC分类号： G11C7/18 , G11C29/34 , G11C2029/1204 , G11C2029/2602
摘要： An integrated memory includes memory cells arranged in a memory cell array along word lines and bit lines. One of the bit lines can be connected to a data line by a respective one of a plurality of switches. The memory contains column select lines. One of the column select lines in each case connected to a plurality of the switches for driving, in an activated state, in order to connect a number of bit lines to a same number of data lines. An access controller is connected to the column select lines and can be operated in a test operating mode such that a plurality of the column select lines are activated in the event of a memory cell access. The writing of test data to the memory cell array in a test operating mode can thus be optimized in accordance with the invention.
摘要翻译： 集成存储器包括沿着字线和位线布置在存储单元阵列中的存储器单元。 其中一个位线可以通过多个开关中的相应一个连接到数据线。 内存包含列选择行。 每种情况下的列选择线之一连接到多个开关，用于在激活状态下驱动，以将多个位线连接到相同数量的数据线。 访问控制器连接到列选择线，并且可以在测试操作模式下操作，使得在存储器单元访问的情况下多个列选择线被激活。 因此可以根据本发明优化将测试数据写入测试操作模式的存储单元阵列。
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2.发明授权公开(公告)号：US07180799B2
公开(公告)日：2007-02-20
申请号：US10948557
申请日：2004-09-24
IPC分类号： G11C7/00
CPC分类号： G11C7/1045
摘要： A circuit for setting one of a plurality of organization forms of an integrated circuit includes a detector circuit connected to an external connection of the integrated circuit. The external connection in at least one of the organization forms can be used for external communication of the integrated circuit. A signal can be impressed into a signal path connected to the external connection by the detector circuit. As a consequence, an output signal is generated at an output of the detector circuit. A control circuit sets one of the organization forms and receives the output signal of the detector circuit. One of the organization forms is set by the control circuit depending on the state of the output signal of the detector circuit. A module with a detector circuit can identify that organization form of the organization forms in which it is operated in the application.
摘要翻译： 用于设置集成电路的多个组织形式之一的电路包括连接到集成电路的外部连接的检测器电路。 组织形式中的至少一个的外部连接可用于集成电路的外部通信。 信号可以通过检测器电路加到连接到外部连接的信号路径中。 因此，在检测器电路的输出处产生输出信号。 控制电路设置组织形式之一并接收检测器电路的输出信号。 组织形式之一由控制电路根据检测器电路的输出信号的状态设置。 具有检测器电路的模块可以识别其在应用中操作的组织形式的组织形式。
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公开(公告)号：US07283419B2
公开(公告)日：2007-10-16
申请号：US11414554
申请日：2006-05-01
IPC分类号： G11C8/00
CPC分类号： G11C7/1045 , G11C7/20 , G11C8/12 , G11C11/4072 , G11C11/408
摘要： An integrated semiconductor memory device includes a first memory zone, a second memory zone, first address connections and a second address connection. A second address signal present at the second address connection specifies the access to the first or second memory zone, whereas it is specified via first address signals at the first address connections which memory cell is accessed within the first or second memory zone. In a first memory configuration, all address connections are driven externally with address signals and the access to a memory cell in the first or second memory zone is controlled. In a second memory configuration, only the first address connections are driven externally whereas a signaling bit in a mode register regulates the access to the first or second memory zone. This provides for access to the second memory zone even if there is no possibility of externally driving the second address connection.
摘要翻译： 集成半导体存储器件包括第一存储区，第二存储区，第一地址连接和第二地址连接。 存在于第二地址连接处的第二地址信号指定对第一或第二存储器区域的访问，而通过第一地址连接处的第一地址信号指定在第一或第二存储器区域内访问哪个存储器单元。 在第一存储器配置中，所有地址连接由地址信号从外部驱动，并且控制对第一或第二存储器区域中的存储器单元的访问。 在第二存储器配置中，仅第一地址连接从外部驱动，而模式寄存器中的信令位调节对第一或第二存储器区的访问。 即使不存在外部驱动第二地址连接的可能性，也可以访问第二存储区域。
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4.发明授权公开(公告)号：US07102362B2
公开(公告)日：2006-09-05
申请号：US10920204
申请日：2004-08-18
IPC分类号： G01R27/06 , G01R31/3185 , G11C29/04
CPC分类号： G11C29/56 , G01R31/2884 , G11C11/401 , G11C29/48 , G11C2029/5602
摘要： An integrated circuit includes a first circuit component, a second circuit component, and an external terminal for making contact with the circuit. The first circuit component is connected to the external terminal via the second component. A bridging circuit connects the first circuit component to the external terminal and can be activated by a test mode signal. In the active state, the bridging circuit connects the external terminal to the first circuit component while bridging the second circuit component, while it is nonconducting in the deactivated state. Circuit components integrated in the semiconductor chip can be electrically measured nondestructively via activatable switches. Circuit components that lie between the external terminal and the device to be measured can be excluded from the measurement by bridging circuits. The method also makes it possible to measure a plurality of integrated devices in parallel or serially.
摘要翻译： 集成电路包括第一电路部件，第二电路部件和用于与电路接触的外部端子。 第一电路部件经由第二部件与外部端子连接。 桥接电路将第一电路组件连接到外部端子，并且可以通过测试模式信号来激活。 在激活状态下，桥接电路将外部端子连接到第一电路部件，同时桥接第二电路部件，同时其处于非导通状态。 集成在半导体芯片中的电路元件可以通过可激活开关非破坏性地电测量。 位于外部端子和待测量器件之间的电路元件可以通过桥接电路从测量中排除。 该方法还使得可以并行或串行地测量多个集成器件。
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公开(公告)号：US07427202B2
公开(公告)日：2008-09-23
申请号：US11317638
申请日：2005-12-22
IPC分类号： H01R12/00
CPC分类号： H01R13/2407 , H01L23/49811 , H01L2224/81897 , H01L2924/0002 , H01L2924/3011 , H01R12/7041 , H01R13/627 , H05K3/305 , H05K3/325 , H05K3/4015 , H05K2201/0373 , H05K2201/10719 , H05K2201/209 , H01L2924/00
摘要： A means of attachment for electrically contacting electronic components is disclosed. The means of attachment includes a carrier element and a number of elongated connecting elements. Each of the connecting elements is arranged on the carrier element and has an elongated body, which protrudes from the carrier element. Each of the connecting elements and the carrier element includes an electrically conductive surface.
摘要翻译： 公开了一种用于电接触电子部件的连接装置。 附接装置包括载体元件和多个细长的连接元件。 每个连接元件布置在载体元件上并且具有从载体元件突出的细长主体。 每个连接元件和载体元件包括导电表面。
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公开(公告)号：US07355218B2
公开(公告)日：2008-04-08
申请号：US11202634
申请日：2005-08-12
IPC分类号： H01L27/10
CPC分类号： H01L27/092 , H01L21/765 , H01L21/823878
摘要： The source area (3) is highly doped, like the channel area, for the same conductance type. The drain area (4) is doped for the opposite conductance type. This results in a saving of area since the source connection (S) can at the same time be used as the well connection or substrate connection.
摘要翻译： 对于相同的电导型，源极区域（3）像沟道区域一样被高度掺杂。 漏极区域（4）被掺杂用于相反的电导型。 这导致节省面积，因为源连接（S）可以同时用作阱连接或衬底连接。
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7.发明授权Semiconductor device, a method of using a semiconductor device, a programmable memory device, and method of producing a semiconductor device 有权半导体器件，使用半导体器件的方法，可编程存储器件以及半导体器件的制造方法公开(公告)号：US07961514B2
公开(公告)日：2011-06-14
申请号：US12349694
申请日：2009-01-07
IPC分类号： G11C16/04
CPC分类号： H01L27/11521 , G11C16/0483 , G11C16/26 , H01L27/11519 , H01L27/11568 , H01L29/7881 , H01L29/792
摘要： A semiconductor device is described. A channel area is arranged in a semiconductor substrate between a first contact area and a second contact area. A first programmable structure includes a first control structure. The first programmable structure is arranged such that a conductivity of a first section of the channel area depends on a voltage applicable to the first control structure of the first programmable structure and on an information value stored in the first programmable structure. A second programmable structure includes a second control structure. The second programmable structure is arranged such that a conductivity of a second section of the channel area depends on a voltage applicable to the second control structure of the second programmable structure and on an information value stored in the second programmable structure. The first section and the second section of the channel area are electrically connected in series between the first contact area and the second contact area.
摘要翻译： 描述半导体器件。 沟道区域布置在第一接触区域和第二接触区域之间的半导体衬底中。 第一可编程结构包括第一控制结构。 第一可编程结构被布置成使得通道区域的第一部分的电导率取决于可应用于第一可编程结构的第一控制结构的电压以及存储在第一可编程结构中的信息值。 第二可编程结构包括第二控制结构。 第二可编程结构被布置成使得通道区域的第二部分的电导率取决于可应用于第二可编程结构的第二控制结构的电压以及存储在第二可编程结构中的信息值。 通道区域的第一部分和第二部分串联地电连接在第一接触区域和第二接触区域之间。
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公开(公告)号：US07330047B2
公开(公告)日：2008-02-12
申请号：US11033988
申请日：2005-01-13
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/00384
摘要： A receiver circuit arrangement includes a receiver circuit an input for receiving an input signal an output for outputting an output signal and an inverter circuit with switching transistors. The input signal is fed to the receiver circuit. At least one control transistor is connected in series with the switching transistors. A control circuit is connected on the input side to a terminal for a reference voltage and on the output side to the control terminal of the control transistor of the inverter circuit. The control circuit is designed such that the control transistor is driven by the regulating switching circuit in the event of deviations of the reference voltage from a voltage value in a reference operating state with a control voltage that deviates with respect to the reference operating state.
摘要翻译： 接收器电路装置包括：接收器电路，用于接收输入信号用于输出输出信号的输出和具有开关晶体管的反相器电路的输入。 输入信号被馈送到接收器电路。 至少一个控制晶体管与开关晶体管串联连接。 控制电路在输入侧连接到用于参考电压的端子，并且在输出侧连接到逆变器电路的控制晶体管的控制端子。 控制电路被设计成使得控制晶体管在参考电压与基准操作状态下的电压值偏离并且相对于参考运行状态偏离的控制电压的情况下由调节开关电路驱动。
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公开(公告)号：US07304899B2
公开(公告)日：2007-12-04
申请号：US11234383
申请日：2005-09-26
IPC分类号： G11C7/00
CPC分类号： G11C7/20 , G11C29/40 , G11C29/44 , G11C29/802 , G11C29/812 , G11C2029/1208 , G11C2029/4402
摘要： An integrated semiconductor memory includes programmable elements, which are arranged in a continuous region on a chip area of the integrated semiconductor memory. Operating parameters, for example, word line addresses of defective word lines are stored in the programmable elements in a compressed data format during the fabrication process of the integrated semiconductor memory. Upon activation of the integrated semiconductor memory, the compressed data are read out by a read-out circuit and fed to a decompression circuit. The decompression circuit generates, from a bit sequence of the compressed data with the aid of a decompression algorithm, a bit sequence of decompressed data which are evaluated by a control circuit. The storage of the operating parameters in the compressed data format and the arrangement of the programmable elements in a compact region significantly reduce the space requirement on the semiconductor chip.
摘要翻译： 集成半导体存储器包括布置在集成半导体存储器的芯片区域上的连续区域中的可编程元件。 在集成半导体存储器的制造过程期间，操作参数例如缺陷字线的字线地址以压缩数据格式存储在可编程元件中。 在激活集成半导体存储器时，通过读出电路读出压缩数据并将其馈送到解压缩电路。 解压缩电路借助于解压缩算法从压缩数据的比特序列生成由控制电路评估的解压缩数据的比特序列。 压缩数据格式中的操作参数的存储和紧凑区域中可编程元件的布置显着地减小了半导体芯片上的空间需求。
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公开(公告)号：US07274218B2
公开(公告)日：2007-09-25
申请号：US11135642
申请日：2005-05-24
IPC分类号： H03K19/094
CPC分类号： H03K19/018521
摘要： An integrated circuit includes a first and a second amplifier circuit (10, 20), which are in each case driven by an input signal (Vin) having a high and a low signal level and a reference signal (Vref) having a constant signal level and, on the output side (D11, D21) generate a first control signal (S1) and a second control signal (S2). The control signals (S1, S2) are generated independently of one another and are used to regulate a first controllable resistor (31) and a second controllable resistor (32) of a third amplifier circuit (30). Depending on the resistance value of the first and second controllable resistors (31, 32) of the third amplifier circuit, an output signal (Vout) that is amplified in comparison with the input signal (Vin) can be generated at an output terminal (A). The integrated circuit can be used as an input amplifier of an integrated semiconductor memory and permits an adaptive behavior of the input amplifier with regard to fluctuations of the average absolute input signal level.
摘要翻译： 集成电路包括第一和第二放大器电路（10,20），它们在每种情况下由具有高和低信号电平的输入信号（Vin）和具有恒定信号电平的参考信号（Vref）驱动 并且在输出侧（D 11，D 21）产生第一控制信号（S 1）和第二控制信号（S 2）。 控制信号（S1，S2）彼此独立地产生，并且用于调节第三放大器电路（30）的第一可控电阻（31）和第二可控电阻（32）。 根据第三放大电路的第一和第二可控电阻（31,32）的电阻值，与输入信号（Vin）相比放大的输出信号（Vout）可以在输出端（A ）。 集成电路可以用作集成半导体存储器的输入放大器，并且允许输入放大器关于平均绝对输入信号电平的波动的自适应行为。
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