-
1.发明授权Double patterning method for creating a regular array of pillars with dual shallow trench isolation 有权双重图案化方法，用于创建具有双浅沟槽隔离的规则的柱状阵列公开(公告)号：US08921196B2
公开(公告)日：2014-12-30
申请号：US13132602
申请日：2008-12-30
IPC分类号： H01L27/102 , H01L27/24 , H01L21/033 , H01L45/00
CPC分类号： H01L27/2463 , H01L21/0338 , H01L21/76224 , H01L27/1022 , H01L27/2445 , H01L29/0649 , H01L29/41708 , H01L29/42304 , H01L29/66272 , H01L29/732 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要： A method is disclosed for forming vertical bipolar junction transistors including a regular array of base contact pillars and emitter contact pillars with a width below the minimum lithographical resolution F of the lithographic technique employed. In an embodiment, the pillar array features have a dimension of approximately F/2, though this dimension could be reduced down to other values compatible with embodiments of the invention. A storage element, such as a phase change storage element, can be formed above the regular array of base contact pillars and emitter contact pillars.
摘要翻译： 公开了用于形成垂直双极结晶体管的方法，其包括基本接触柱的规则阵列和具有低于所采用的光刻技术的最小光刻分辨率F的宽度的发射极接触柱。 在一个实施例中，柱阵列特征具有大约F / 2的尺寸，尽管该尺寸可以减小到与本发明的实施例相容的其它值。 诸如相变存储元件的存储元件可以形成在基底接触柱和发射极接触柱的规则阵列上方。
-
2.发明申请DOUBLE PATTERNING METHOD FOR CREATING A REGULAR ARRAY OF PILLARS WITH DUAL SHALLOW TRENCH ISOLATION 有权用于创建具有双壁分离分离柱的常规阵列的双重图案方法公开(公告)号：US20110248382A1
公开(公告)日：2011-10-13
申请号：US13132602
申请日：2008-12-30
IPC分类号： H01L27/102 , H01L21/8229
CPC分类号： H01L27/2463 , H01L21/0338 , H01L21/76224 , H01L27/1022 , H01L27/2445 , H01L29/0649 , H01L29/41708 , H01L29/42304 , H01L29/66272 , H01L29/732 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要： A method is disclosed for forming vertical bipolar junction transistors including a regular array of base contact pillars and emitter contact pillars with a width below the minimum lithographical resolution F of the lithographic technique employed. In an embodiment, the pillar array features have a dimension of approximately F/2, though this dimension could be reduced down to other values compatible with embodiments of the invention. A storage element, such as a phase change storage element, can be formed above the regular array of base contact pillars and emitter contact pillars.
摘要翻译： 公开了用于形成垂直双极结晶体管的方法，其包括基本接触柱的规则阵列和具有低于所采用的光刻技术的最小光刻分辨率F的宽度的发射极接触柱。 在一个实施例中，柱阵列特征具有大约F / 2的尺寸，尽管该尺寸可以减小到与本发明的实施例相容的其它值。 诸如相变存储元件的存储元件可以形成在基底接触柱和发射极接触柱的规则阵列上方。
-
公开(公告)号：US20100308296A1
公开(公告)日：2010-12-09
申请号：US12481496
申请日：2009-06-09
CPC分类号： H01L45/06 , H01L27/2445 , H01L27/2463 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1675
摘要： A self-aligned vertical heater element is deposited directly on the silicide of a selection device, and a phase change chalcogenide material is deposited directly on the vertical heater element. The fabrication process allows for self-alignment between the chalcogenide line and vertical heater element. In an embodiment, the vertical heater element is L-shaped, having a vertical wall along the wordline direction and a horizontal base. The vertical wall and the horizontal base may have the same thickness.
摘要翻译： 自对准垂直加热元件直接沉积在选择装置的硅化物上，相变硫族化物材料直接沉积在垂直加热元件上。 制造工艺允许硫族化物管线和垂直加热器元件之间的自对准。 在一个实施例中，垂直加热器元件是L形的，具有沿字线方向的垂直壁和水平底座。 垂直壁和水平底座可以具有相同的厚度。
-
4.发明申请公开(公告)号：US20110039391A1
公开(公告)日：2011-02-17
申请号：US12912829
申请日：2010-10-27
IPC分类号： H01L21/331
摘要： A bipolar junction transistor may act as a select device for a semiconductor memory. The bipolar junction transistor may be formed of a stack of base and collector layers. Sets of parallel trenches are formed in a first direction down to the base and in a second direction down to the collector. The trenches may be used to form local enhancement implants into the exposed portion of the base and collector in each trench. As a result of the local enhancement implants, in some embodiments, leakage current may be reduced, active current capability may be higher, gain may be higher, base resistance may be reduced, breakdown voltage may be increased, and parasitic effects with adjacent junctions may be reduced.
摘要翻译： 双极结型晶体管可以用作半导体存储器的选择器件。 双极结晶体管可以由基极和集电极层的堆叠形成。 一组平行的沟槽沿着第一方向下降到底部并且沿着第二方向形成在收集器的下方。 沟槽可以用于在每个沟槽中的基底和收集器的暴露部分中形成局部增强植入物。 作为局部增强植入物的结果，在一些实施例中，泄漏电流可能降低，有效电流能力可能更高，增益可能更高，基极电阻可能降低，击穿电压可能增加，并且具有相邻接点的寄生效应 减少
-
5.发明授权公开(公告)号：US08076211B2
公开(公告)日：2011-12-13
申请号：US12912829
申请日：2010-10-27
IPC分类号： H01L21/8222 , H01L21/331
摘要： A bipolar junction transistor may act as a select device for a semiconductor memory. The bipolar junction transistor may be formed of a stack of base and collector layers. Sets of parallel trenches are formed in a first direction down to the base and in a second direction down to the collector. The trenches may be used to form local enhancement implants into the exposed portion of the base and collector in each trench. As a result of the local enhancement implants, in some embodiments, leakage current may be reduced, active current capability may be higher, gain may be higher, base resistance may be reduced, breakdown voltage may be increased, and parasitic effects with adjacent junctions may be reduced.
摘要翻译： 双极结型晶体管可以用作半导体存储器的选择器件。 双极结晶体管可以由基极和集电极层的堆叠形成。 一组平行的沟槽沿着第一方向下降到底部并且沿着第二方向形成在收集器的下方。 沟槽可以用于在每个沟槽中的基底和收集器的暴露部分中形成局部增强植入物。 作为局部增强植入物的结果，在一些实施例中，泄漏电流可能降低，有效电流能力可能更高，增益可能更高，基极电阻可能降低，击穿电压可能增加，并且具有相邻接点的寄生效应 减少
-
6.发明授权公开(公告)号：US07847373B2
公开(公告)日：2010-12-07
申请号：US12341027
申请日：2008-12-22
IPC分类号： H01L27/082 , H01L27/102 , H01L29/70
摘要： A bipolar junction transistor may act as a select device for a semiconductor memory. The bipolar junction transistor may be formed of a stack of base and collector layers. Sets of parallel trenches are formed in a first direction down to the base and in a second direction down to the collector. The trenches may be used to form local enhancement implants into the exposed portion of the base and collector in each trench. As a result of the local enhancement implants, in some embodiments, leakage current may be reduced, active current capability may be higher, gain may be higher, base resistance may be reduced, breakdown voltage may be increased, and parasitic effects with adjacent junctions may be reduced.
摘要翻译： 双极结型晶体管可以用作半导体存储器的选择器件。 双极结晶体管可以由基极和集电极层的堆叠形成。 一组平行的沟槽沿着第一方向下降到底部并且沿着第二方向形成在收集器的下方。 沟槽可以用于在每个沟槽中的基底和收集器的暴露部分中形成局部增强植入物。 作为局部增强植入物的结果，在一些实施例中，泄漏电流可能降低，有效电流能力可能更高，增益可能更高，基极电阻可能降低，击穿电压可能增加，并且具有相邻接点的寄生效应 减少
-
公开(公告)号：US20120032136A1
公开(公告)日：2012-02-09
申请号：US12849864
申请日：2010-08-04
CPC分类号： H01L45/06 , H01L23/5256 , H01L27/2445 , H01L27/2463 , H01L45/12 , H01L45/1226 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16 , H01L45/1675 , H01L45/1683
摘要： A resistive random access memory array may be formed on the same substrate with a fuse array. The random access memory and the fuse array may use the same active material. For example, both the fuse array and the memory array may use a chalcogenide material as the active switching material. The main array may use a pattern of perpendicular sets of trench isolations and the fuse array may only use one set of parallel trench isolations. As a result, the fuse array may have a conductive line extending continuously between adjacent trench isolations. In some embodiments, this continuous line may reduce the resistance of the conductive path through the fuses.
摘要翻译： 可以在具有熔丝阵列的同一基板上形成电阻随机存取存储器阵列。 随机存取存储器和熔丝阵列可以使用相同的活性材料。 例如，熔丝阵列和存储器阵列都可以使用硫族化物材料作为有源开关材料。 主阵列可以使用垂直组沟槽隔离的图案，并且熔丝阵列可以仅使用一组平行沟槽隔离。 结果，熔丝阵列可以具有在相邻沟槽隔离之间连续延伸的导电线。 在一些实施例中，该连续线可以减小通过保险丝的导电路径的电阻。
-
8.发明申请PROCESS FOR FORMING DIFFERENTIAL SPACES IN ELECTRONICS DEVICE INTEGRATED ON A SEMICONDUCTOR SUBSTRATE 有权在半导体基板上集成的电子器件中形成差分空间的方法公开(公告)号：US20100047980A1
公开(公告)日：2010-02-25
申请号：US12606997
申请日：2009-10-27
申请人： Giorgio Servalli , Giulio Albini , Carlo Cremonesi
发明人： Giorgio Servalli , Giulio Albini , Carlo Cremonesi
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11546 , H01L29/66553
摘要： A forms spacers in a electronic device integrated on a semiconductor substrate that includes: first and second transistors each comprising a gate electrode projecting from the substrate and respective source/drain regions. The process comprises: forming in cascade a first protective layer and a first conformal insulating layer of a first thickness on the whole electronic device; forming a first mask to cover the first transistor; removing the first conformal insulating layer not covered by the first mask; removing the first mask; forming a second conformal insulating layer of a second thickness on the whole device; and removing the insulating layers until the protective layer is exposed to form first spacers of a first width on the side walls of the gate electrodes of the first transistor and second spacers of a second width on the side walls of the gate electrodes of the second transistor.
摘要翻译： A在集成在半导体衬底上的电子器件中形成间隔物，其包括：第一和第二晶体管，每个包括从衬底突出的栅电极和相应的源极/漏极区。 该方法包括：在整个电子设备上级联形成第一厚度的第一保护层和第一共形绝缘层; 形成第一掩模以覆盖所述第一晶体管; 去除未被第一掩模覆盖的第一保形绝缘层; 去除第一个面罩; 在整个装置上形成第二厚度的第二共形绝缘层; 并且去除所述绝缘层直到所述保护层暴露以在所述第一晶体管的栅电极的侧壁上形成第一宽度的第一间隔物，并且在所述第二晶体管的栅电极的侧壁上形成第二宽度的第二间隔物 。
-
9.发明申请PROCESS FOR FORMING DIFFERENTIAL SPACES IN ELECTRONICS DEVICE INTEGRATED ON A SEMICONDUCTOR SUBSTRATE 审中-公开在半导体基板上集成的电子器件中形成差分空间的方法公开(公告)号：US20080206945A1
公开(公告)日：2008-08-28
申请号：US11680507
申请日：2007-02-28
申请人： Giorgio Servalli , Giulio Albini , Carlo Cremonesi
发明人： Giorgio Servalli , Giulio Albini , Carlo Cremonesi
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11546 , H01L29/66553
摘要： A forms spacers in a electronic device integrated on a semiconductor substrate that includes: first and second transistors each comprising a gate electrode projecting from the substrate and respective source/drain regions. The process comprises: forming in cascade a first protective layer and a first conformal insulating layer of a first thickness on the whole electronic device; forming a first mask to cover the first transistor; removing the first conformal insulating layer not covered by the first mask; removing the first mask; forming a second conformal insulating layer of a second thickness on the whole device; and removing the insulating layers until the protective layer is exposed to form first spacers of a first width on the side walls of the gate electrodes of the first transistor and second spacers of a second width on the side walls of the gate electrodes of the second transistor.
摘要翻译： A在集成在半导体衬底上的电子器件中形成间隔物，其包括：第一和第二晶体管，每个包括从衬底突出的栅电极和相应的源极/漏极区。 该方法包括：在整个电子设备上级联形成第一厚度的第一保护层和第一共形绝缘层; 形成第一掩模以覆盖所述第一晶体管; 去除未被第一掩模覆盖的第一保形绝缘层; 去除第一个面罩; 在整个装置上形成第二厚度的第二共形绝缘层; 并且去除所述绝缘层直到所述保护层暴露以在所述第一晶体管的栅电极的侧壁上形成第一宽度的第一间隔物，并且在所述第二晶体管的栅电极的侧壁上形成第二宽度的第二间隔物 。
-
公开(公告)号：US20070181933A1
公开(公告)日：2007-08-09
申请号：US11617472
申请日：2006-12-28
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L27/0203 , H01L27/11521
摘要： A non-volatile memory device integrated on semiconductor substrate and having a matrix of non-volatile memory cells organized in rows, called word lines, and columns, called bit lines, the device including a plurality of active areas formed on the semiconductor substrate equidistant from each other, and having at least a first and a second group of active areas; the non-volatile memory cells integrated in the first group of active areas, each non-volatile memory cell having a source region, a drain region, and a floating gate electrode coupled to a control gate electrode, at least one group of the memory cells sharing a common source region integrated on the semiconductor substrate; and a contact region integrated in the second group of active areas and provided with at least one common source contact of the common source region.
摘要翻译： 一种非易失性存储器件，集成在半导体衬底上并且具有被称为位线的被称为字线的行（称为字线）和列的非易失性存储器单元矩阵，该器件包括形成在半导体衬底上等距离的多个有源区 并且具有至少第一组和第二组活动区域; 集成在第一组有源区域中的非易失性存储单元，每个非易失性存储单元具有耦合到控制栅电极的源极区，漏极区和浮栅，至少一组存储单元 共享在半导体衬底上集成的公共源极区域; 以及集成在所述第二组有源区域中并且设置有所述公共源极区域的至少一个公共源极触点的接触区域。
-
-
-
-
-
-
-
-
-
搜索结果
37 条记录 (耗时 0.019 秒)
