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公开(公告)号：US20130339670A1
公开(公告)日：2013-12-19
申请号：US13524356
申请日：2012-06-15
IPC分类号： G06F9/30
CPC分类号： G06F9/3838 , G06F9/30043 , G06F9/3017 , G06F9/3834
摘要： Embodiments relate to reducing operand store compare penalties by detecting potential unit of operation (UOP) dependencies. An aspect includes a computer system for reducing operation store compare penalties. The system includes memory and a processor. The system performs a method including cracking an instruction into units of operation, where each UOP includes instruction text and address determination fields. The method includes identifying a load UOP among the plurality of UOPs and comparing values of the address determination fields of the load UOP with values of address determination fields of one or more previously-decoded store UOPs. The method also includes forcing, prior to issuance of the instruction to an execution unit, a dependency between the load UOP and the one or more previously-decoded store UOPs based on the comparing.
摘要翻译： 实施例涉及通过检测潜在的操作单元（UOP）依赖性来减少操作数存储比较处罚。 一方面包括用于减少操作存储比较处罚的计算机系统。 该系统包括内存和处理器。 系统执行包括将指令分解为操作单元的方法，其中每个UOP包括指令文本和地址确定字段。 该方法包括识别多个UOP之间的负载UOP，并将负载UOP的地址确定字段的值与一个或多个先前解码的存储UOP的地址确定字段的值进行比较。 该方法还包括在向执行单元发出指令之前强迫基于该比较的加载UOP和一个或多个先前解码的存储UOP之间的依赖关系。
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公开(公告)号：US09626189B2
公开(公告)日：2017-04-18
申请号：US13524356
申请日：2012-06-15
CPC分类号： G06F9/3838 , G06F9/30043 , G06F9/3017 , G06F9/3834
摘要： Embodiments relate to reducing operand store compare penalties by detecting potential unit of operation (UOP) dependencies. An aspect includes a computer system for reducing operation store compare penalties. The system includes memory and a processor. The system performs a method including cracking an instruction into units of operation, where each UOP includes instruction text and address determination fields. The method includes identifying a load UOP among the plurality of UOPs and comparing values of the address determination fields of the load UOP with values of address determination fields of one or more previously-decoded store UOPs. The method also includes forcing, prior to issuance of the instruction to an execution unit, a dependency between the load UOP and the one or more previously-decoded store UOPs based on the comparing.
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公开(公告)号：US07200742B2
公开(公告)日：2007-04-03
申请号：US11055193
申请日：2005-02-10
申请人： Fadi Y. Busaba , Michael J. Mack , John G. Rell, Jr. , Eric M. Schwarz , Chung-Lung K. Shum , Timothy J. Slegel , Scott B. Swaney , Sheryll H. Veneracion
发明人： Fadi Y. Busaba , Michael J. Mack , John G. Rell, Jr. , Eric M. Schwarz , Chung-Lung K. Shum , Timothy J. Slegel , Scott B. Swaney , Sheryll H. Veneracion
IPC分类号： G06F9/38
CPC分类号： G06F9/4812 , G06F9/30101 , G06F9/3863 , G06F2209/481
摘要： A method for creating precise exceptions including checkpointing an exception causing instruction. The checkpointing results in a current checkpointed state. The current checkpointed state is locked. It is determined if any of a plurality of registers require restoration to the current checkpointed state. One or more of the registers are restored to the current checkpointed state in response to the results of the determining indicating that the one or more registers require the restoring. The execution unit is restarted at the exception handler or the next sequential instruction dependent on whether traps are enabled for the exception.
摘要翻译： 一种用于创建精确异常的方法，包括检查指向引起异常的指令。 检查点导致当前检查点状态。 当前检查点状态被锁定。 确定多个寄存器中的任一个是否需要恢复到当前检查点状态。 响应于指示一个或多个寄存器需要恢复的确定结果，一个或多个寄存器恢复到当前检查点状态。 执行单元在异常处理程序或下一个顺序指令下重新启动，取决于是否为异常启用陷阱。
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公开(公告)号：US09891922B2
公开(公告)日：2018-02-13
申请号：US13524402
申请日：2012-06-15
CPC分类号： G06F9/38 , G06F9/30076 , G06F9/3844 , G06F9/3848
摘要： Embodiments relate to selectively blocking branch instruction predictions. An aspect includes a computer system for performing selective branch prediction. The system includes memory and a processor, and the system is configured to perform a method. The method includes detecting a branch-prediction blocking instruction in a stream of instructions and blocking branch prediction of a predetermined number of branch instructions following the branch-prediction blocking instruction based on the detecting the branch-prediction blocking instruction.
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公开(公告)号：US09465716B2
公开(公告)日：2016-10-11
申请号：US13422532
申请日：2012-03-16
CPC分类号： G06F11/3466 , G06F9/3005 , G06F11/3636 , G06F11/3644 , G06F11/3648
摘要： The invention relates to implementing run-time instrumentation directed sampling. An aspect of the invention includes fetching a run-time instrumentation next (RINEXT) instruction from an instruction stream. The instruction stream includes the RINEXT instruction followed by a next sequential instruction (NSI) in program order. The method further includes executing the RINEXT instruction by a processor. The executing includes determining whether a current run-time instrumentation state enables setting a sample point for reporting run-time instrumentation information during program execution. Based on the current run-time instrumentation state enabling setting the sample point, the NSI is a sample instruction for causing a run-time instrumentation event. Based on executing the NSI sample instruction, the run-time instrumentation event causes recording of run-time instrumentation information into a run-time instrumentation program buffer as a reporting group.
摘要翻译： 本发明涉及实施运行时仪表定向抽样。 本发明的一个方面包括从指令流获取运行时仪器下一个（RINEXT）指令。 指令流包括RINEXT指令，后面是程序顺序的下一个顺序指令（NSI）。 该方法还包括由处理器执行RINEXT指令。 该执行包括确定当前运行时仪表状态是否能够在程序执行期间设置用于报告运行时仪表信息的采样点。 根据当前的运行时仪器状态设置采样点，NSI是一个用于引起运行时仪表事件的示例指令。 基于执行NSI示例指令，运行时仪表事件将运行时仪表信息记录到作为报告组的运行时仪表程序缓冲区中。
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公开(公告)号：US09454462B2
公开(公告)日：2016-09-27
申请号：US13422542
申请日：2012-03-16
申请人： Mark S. Farrell , Charles W. Gainey, Jr. , Marcel M. Mitran , Damian L. Osisek , Chung-Lung K. Shum , Timothy J. Slegel , Brian L. Smith
发明人： Mark S. Farrell , Charles W. Gainey, Jr. , Marcel M. Mitran , Damian L. Osisek , Chung-Lung K. Shum , Timothy J. Slegel , Brian L. Smith
CPC分类号： G06F9/30145 , G06F9/3005 , G06F9/45533 , G06F11/3466 , G06F11/348 , G06F11/3644 , G06F2201/86 , G06F2201/88
摘要： The invention relates to monitoring processor characteristic information of a processor using run-time-instrumentation. An aspect of the invention includes executing an instruction stream on the processor and detecting a run-time instrumentation sample point of the executing instruction stream on the processor. A reporting group is stored in a run-time instrumentation program buffer based on the run-time instrumentation sample point. The reporting group includes processor characteristic information associated with the processor.
摘要翻译： 本发明涉及使用运行时间仪器监视处理器的处理器特性信息。 本发明的一个方面包括在处理器上执行指令流并检测处理器上的执行指令流的运行时检测采样点。 基于运行时仪器采样点，报告组存储在运行时仪表程序缓冲区中。 报告组包括与处理器相关联的处理器特性信息。
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公开(公告)号：US09152518B2
公开(公告)日：2015-10-06
申请号：US13353544
申请日：2012-01-19
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
摘要： A re-characterization process is provided that adjusts one or more operating parameters of a processor to improve the health (e.g., reduce errors) of the processor. The parameters include voltage and/or clock frequency, as examples. The processor can be an inactive or active processor for which the re-characterization process is performed. It is performed, in one instance, by a hardware controller in real-time.
摘要翻译： 提供了重新表征处理，其调整处理器的一个或多个操作参数以改善处理器的健康状况（例如，减少错误）。 参数包括电压和/或时钟频率，例如。 处理器可以是对其执行重新表征处理的非活动或活动处理器。 在一个实例中，它由硬件控制器实时执行。
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公开(公告)号：US08954797B2
公开(公告)日：2015-02-10
申请号：US13447554
申请日：2012-04-16
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
CPC分类号： G06F11/1446 , G06F1/3287 , G06F11/0772 , G06F11/0781 , G06F11/0793 , G06F11/1407 , G06F11/1425 , G06F11/1428 , Y02D10/171
摘要： A computer program product for performing error recovery is configured to perform a method that includes creating, by a processor, a recovery checkpoint. The processor is dynamically switched into a non-recoverable processing mode of operation based on creating the software recovery checkpoint. The non-recoverable processing mode of operation is a mode in which a subset of hardware error recovery resources are powered-down or re-purposed for instruction processing. It is determined, during the non-recoverable processing mode of operation, that a new software recovery checkpoint is required. Based on the determining that a new software recovery checkpoint is required, the processor is dynamically switched into a recoverable processing mode of operation. The recoverable processing mode of operation is a mode in which hardware error recovery resources, including at least one of the hardware error recovery resources in the subset, are purposed for hardware error recovery operations.
摘要翻译： 用于执行错误恢复的计算机程序产品被配置为执行包括由处理器创建恢复检查点的方法。 基于创建软件恢复检查点，处理器被动态切换到不可恢复的处理操作模式。 不可恢复的处理操作模式是硬件错误恢复资源的子集被掉电或重新用于指令处理的模式。 在不可恢复的处理操作模式下，确定需要新的软件恢复检查点。 基于确定需要新的软件恢复检查点，处理器被动态切换成可恢复的处理操作模式。 可恢复处理操作模式是硬件错误恢复资源（包括该子集中的至少一个硬件错误恢复资源）用于硬件错误恢复操作的模式。
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公开(公告)号：US08954678B2
公开(公告)日：2015-02-10
申请号：US13523922
申请日：2012-06-15
IPC分类号： G06F12/12
CPC分类号： G06F12/0862 , G06F2212/6024 , G06F2212/6026
摘要： Embodiments relate to automatic pattern-based operand prefetching. An aspect includes receiving, by prefetch logic in a processor, an operand cache miss from a pipeline of the processor. Another aspect includes determining that an entry in a history table corresponding to the operand cache miss exists based on an instruction address of the operand cache miss. Yet another aspect includes, based on determining that the entry corresponding to the operand cache miss exists in the history table, issuing a prefetch instruction for a second operand based on the determined entry in the history table, and writing the determined entry into a miss buffer.
摘要翻译： 实施例涉及自动基于模式的操作数预取。 一个方面包括通过处理器中的预取逻辑从处理器的流水线接收操作数高速缓存未命中。 另一方面包括基于操作数高速缓存未命中的指令地址来确定与操作数高速缓存未命中对应的历史表中的条目。 另一方面包括：基于确定对应于操作数高速缓存未命中的条目存在于历史表中，基于历史表中确定的条目发布第二操作数的预取指令，并将所确定的条目写入未命中缓冲器 。
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公开(公告)号：US20130339683A1
公开(公告)日：2013-12-19
申请号：US13523170
申请日：2012-06-14
申请人： James J. Bonanno , Adam B. Collura , Ulrich Mayer , Brian R. Prasky , Anthony Saporito , Chung-Lung K. Shum
发明人： James J. Bonanno , Adam B. Collura , Ulrich Mayer , Brian R. Prasky , Anthony Saporito , Chung-Lung K. Shum
IPC分类号： G06F9/30
CPC分类号： G06F9/3844 , G06F9/30 , G06F9/30047 , G06F9/3005 , G06F9/3806 , G06F9/3836
摘要： Embodiments relate to instruction filtering. An aspect includes a system for instruction filtering. The system includes memory configured to store instructions accessible by a processor, and the processor includes a tracking array and a tracked instruction logic block. The processor is configured to perform a method including detecting a tracked instruction in an instruction stream, and storing an instruction address of the tracked instruction in the tracking array based on detecting and executing the tracked instruction. The method also includes accessing the tracking array based on an address of instruction data of a subsequently fetched instruction to locate the instruction address of the tracked instruction in the tracking array as an indication of the tracked instruction. Instruction text of the subsequently fetched instruction is marked to indicate previous execution based on the tracking array. An action of the tracked instruction logic block is prevented based on the marked instruction text.
摘要翻译： 实施例涉及指令过滤。 一个方面包括用于指令过滤的系统。 该系统包括被配置为存储由处理器可访问的指令的存储器，并且处理器包括跟踪阵列和跟踪的指令逻辑块。 处理器被配置为执行包括检测指令流中的跟踪指令并且基于检测和执行跟踪指令将追踪指令的指令地址存储在跟踪数组中的方法。 该方法还包括基于随后获取的指令的指令数据的地址来访问跟踪数组，以将跟踪数组中跟踪的指令的指令地址定位为跟踪指令的指示。 随后获取的指令的指令文本被标记为基于跟踪数组指示先前的执行。 基于标记的指令文本来防止跟踪指令逻辑块的动作。
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