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19 条记录 (耗时 0.027 秒)

    High-Q, variable capacitance capacitor
    7.
    发明授权
    High-Q, variable capacitance capacitor 失效
    高Q，可变电容电容

    公开(公告)号：US06587326B2

    公开(公告)日：2003-07-01

    申请号：US10251630

    申请日：2002-09-19

    申请人： Riccardo Depetro ,  Stefano Manzini

    发明人： Riccardo Depetro ,  Stefano Manzini

    IPC分类号： H01G500

    CPC分类号： H01L29/417 ,  H01L29/94

    摘要： High-Q, variable capacitance capacitor is formed by including a pocket of semiconductor material; a field insulating layer, covering the pocket; an opening in the field insulating layer, delimiting a first active area; an access region formed in the active area and extending at a distance from a first edge of the active area and adjacent to a second edge of the active area. A portion of the pocket is positioned between the access region and the first edge and forms a first plate; an insulating region extends above the portion of said body, and a polysilicon region extends above the insulating region and forms a second plate. A portion of the polysilicon region extends above the field insulating layer, parallel to the access region; a plurality of contacts are formed at a mutual distance along the portion of the polysilicon region extending above the field insulating layer.

    摘要翻译： 高Q型可变容性电容器通过包括半导体材料的袋形成; 覆盖口袋的场绝缘层; 在所述场绝缘层中的开口，限定第一有源区; 存取区，形成在有源区中，并且与有源区的第一边缘相距一定距离并且与有源区的第二边相邻。 口袋的一部分位于入口区域和第一边缘之间并形成第一板; 绝缘区域延伸到所述主体的部分上方，并且多晶硅区域延伸到绝缘区域上方并形成第二板。 所述多晶硅区域的一部分在所述场绝缘层的上方延伸，与所述接入区域平行; 沿着在场绝缘层上方延伸的多晶硅区域的相互距离形成多个触点。

    Varactor, in particular for radio-frequency transceivers
    9.
    发明授权
    Varactor, in particular for radio-frequency transceivers 有权
    Varactor，特别是射频收发器

    公开(公告)号：US06400001B1

    公开(公告)日：2002-06-04

    申请号：US09493842

    申请日：2000-01-28

    申请人： Stefano Manzini ,  Pietro Erratico

    发明人： Stefano Manzini ,  Pietro Erratico

    IPC分类号： H01L2993

    CPC分类号： H01L29/94

    摘要： A varactor has a gate region, first and second biasing regions of N+ type embedded in a well, and first and second extraction regions of P+ type, forming a pair of PN junctions with the well. The PN junctions are inversely biased and extract charge accumulating in the well, below the gate region, when the gate region is biased to a lower voltage than a predetermined threshold value.

    摘要翻译： 变容二极管具有栅极区域，嵌入阱中的N +型的第一和第二偏置区域以及P +型的第一和第二提取区域，与阱形成一对PN结。 当栅极区域被偏置到比预定阈值更低的电压时，PN结反向偏置并提取在阱中的阱下面积聚的电荷。

    Integrated circuit with EPROM cells
    10.
    发明授权
    Integrated circuit with EPROM cells 失效
    集成电路与EPROM单元

    公开(公告)号：US5610421A

    公开(公告)日：1997-03-11

    申请号：US358152

    申请日：1994-12-15

    申请人： Claudio Contiero ,  Tiziana Cavioni ,  Stefano Manzini

    发明人： Claudio Contiero ,  Tiziana Cavioni ,  Stefano Manzini

    IPC分类号： H01L21/8247 ,  H01L27/06 ,  H01L27/092 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/105 ,  H01L27/0623 ,  H01L27/0922

    摘要： An integrated circuit structure is disclosed wherein an EPROM cell has an active area formed by the same operations as are carried out to form a P region intended to contain an N-channel MOS transistor, source and drain regions formed by the same operations as are carried out to form the source and drain regions of said transistor, a control electrode consisting of an N+ region formed by the same operations as are carried out to form deep regions intended to contact buried N+ regions, and a floating gate electrode consisting of a layer of conductive material formed by the same operations as are carried out to form the gate electrodes of the MOS transistors in the integrated circuit.The EPROM cell can, therefore, be formed in a mixed integrated circuit with no need for purposely added processing steps.

    摘要翻译： 公开了一种集成电路结构，其中EPROM单元具有通过与用于形成用于包含N沟道MOS晶体管的P区域相同的操作而形成的有源区域，源极和漏极区域通过与所携带的相同的操作形成 以形成所述晶体管的源极和漏极区域，由与进行相同操作形成的N +区域组成的控制电极以形成用于接触掩埋的N +区域的深区域，以及浮栅电极，其由 导电材料通过与集成电路中的MOS晶体管的栅电极相同的操作形成。 因此，可以在混合集成电路中形成EPROM单元，而不需要有意添加的处理步骤。