公开(公告)号：US06699792B1

公开(公告)日：2004-03-02

申请号：US09907398

申请日：2001-07-17

申请人： Fei Wang ,  Lu You ,  Lynne Okada

发明人： Fei Wang ,  Lu You ,  Lynne Okada

IPC分类号： H01L21311

CPC分类号： H01L21/32139 ,  H01L21/0271 ,  H01L21/0338 ,  H01L21/31144

摘要： In forming an opening or space in a substrate, a layer of photoresist is provided on the substrate, and the photoresist is patterned to provide photoresist bodies having respective adjacent sidewalls. A polymer layer is provided on the resulting structure through a low temperature conformal CVD process. The polymer layer is anisotropically etched to form spacers on the respective adjacent sidewalls of the photoresist bodies. The substrate is then etched using the spacers as a mask.

摘要翻译： 在形成衬底中的开口或空间时，在衬底上提供光致抗蚀剂层，并且对光致抗蚀剂进行图案化以提供具有相应相邻侧壁的光致抗蚀剂体。 通过低温保形CVD工艺在所得结构上提供聚合物层。 聚合物层被各向异性蚀刻以在光致抗蚀剂体的各个相邻侧壁上形成间隔物。 然后使用间隔物作为掩模蚀刻衬底。

公开(公告)号：US07001840B1

公开(公告)日：2006-02-21

申请号：US10361332

申请日：2003-02-10

申请人： Minh Quoc Tran ,  Lu You ,  Fei Wang ,  Lynne Okada

发明人： Minh Quoc Tran ,  Lu You ,  Fei Wang ,  Lynne Okada

IPC分类号： H01L21/44

CPC分类号： H01L21/76879 ,  H01L21/2885

摘要： An interconnect structure is formed with a plurality of layers of a conductive material with a grain boundary between any two adjacent layers of the conductive material. Such grain boundaries between layers of conductive material act as shunt by-pass paths for migration of atoms of the conductive material to minimize migration of atoms of the conductive material along the interface between a dielectric passivation or capping layer and the interconnect structure. When the interconnect structure is a via structure, each of the layers of the conductive material and each of the grain boundary are formed to be perpendicular to a direction of current flow through the via structure. Such grain boundaries formed between the plurality of layers of conductive material in the via structure minimize charge carrier wind-force along the direction of current flow through the via structure to further minimize electromigration failure of the via structure.

摘要翻译： 互连结构形成有导电材料的多层，在导电材料的任何两个相邻层之间具有晶界。 导电材料层之间的这种晶界作为用于迁移导电材料的原子的分流旁通路径，以最小化导电材料原子沿着介电钝化层或覆盖层与互连结构之间的界面的迁移。 当互连结构是通孔结构时，导电材料的每个层和每个晶界形成为垂直于通过过孔结构的电流的方向。 在通孔结构中的多个导电材料层之间形成的这种晶界沿着通过通孔结构的电流流动的方向最小化载流子的风力，以进一步最小化通孔结构的电迁移故障。

公开(公告)号：US07256499B1

公开(公告)日：2007-08-14

申请号：US11230985

申请日：2005-09-19

申请人： Lu You ,  Fei Wang ,  Minh Quoc Tran ,  Lynne A. Okada

发明人： Lu You ,  Fei Wang ,  Minh Quoc Tran ,  Lynne A. Okada

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/5226 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit is provided including forming a porous ultra-low dielectric constant dielectric layer over a semiconductor substrate and forming an opening in the ultra-low dielectric constant dielectric layer. A dielectric liner is formed to line the opening to cover the pores in the ultra-low dielectric constant dielectric layer and a barrier layer is deposited to line the dielectric liner and conductor core is deposited to fill the opening over the barrier layer.

摘要翻译： 提供了一种集成电路，包括在半导体衬底上形成多孔超低介电常数介电层，并在超低介电常数介电层中形成开口。 形成电介质衬垫以使开口线对，以覆盖超低介电常数电介质层中的孔，并且沉积阻挡层以对电介质衬垫进行排列，并且沉积导体芯以填充阻挡层上的开口。

公开(公告)号：US07208418B1

公开(公告)日：2007-04-24

申请号：US10728774

申请日：2003-12-08

申请人： Lynne A. Okada ,  Minh Quoc Tran ,  Fei Wang ,  Lu You

发明人： Lynne A. Okada ,  Minh Quoc Tran ,  Fei Wang ,  Lu You

IPC分类号： H01L21/311

CPC分类号： H01L21/76831

摘要： Barrier metal layer discontinuities or gaps due to low-k dielectric porosity is reduced by sealing sidewall porosity before barrier metal layer deposition. Embodiments include sealing sidewall porosity by depositing a swelling agent, adhesion promoter or an additional layer of low-k material.

摘要翻译： 通过在阻挡金属层沉积之前密封侧壁孔隙率来减少由于低k介电孔隙导致的阻挡金属层不连续性或间隙。 实施例包括通过沉积溶胀剂，粘合促进剂或低k材料的附加层来密封侧壁孔隙。

公开(公告)号：US07038320B1

公开(公告)日：2006-05-02

申请号：US09785445

申请日：2001-02-20

申请人： Lu You ,  Fei Wang ,  Minh Van Ngo

发明人： Lu You ,  Fei Wang ,  Minh Van Ngo

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L21/76832 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/76834

摘要： A semiconductor device includes a first metallization layer, a first diffusion barrier layer, a first etch stop layer, a dielectric layer and a via extending through the dielectric layer, the first etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization layer. The first etch stop layer is disposed over and spaced from the first diffusion barrier layer, and the dielectric layer is disposed over the first etch stop layer. The via can also have rounded corners. A second etch stop layer can also be disposed between the first diffusion barrier layer and the first etch stop layer. A sidewall diffusion barrier layer can be disposed on sidewalls of the via, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. A method of manufacturing the semiconductor device is also disclosed.

摘要翻译： 半导体器件包括第一金属化层，第一扩散阻挡层，第一蚀刻停止层，介电层和延伸穿过介电层的通孔，第一蚀刻停止层和第一扩散阻挡层。 第一扩散阻挡层设置在第一金属化层上。 第一蚀刻停止层设置在第一扩散阻挡层上并与第一扩散阻挡层隔开，并且介电层设置在第一蚀刻停止层上。 通孔也可以有圆角。 第二蚀刻停止层也可以设置在第一扩散阻挡层和第一蚀刻停止层之间。 侧壁扩散阻挡层可以设置在通孔的侧壁上，并且侧壁扩散阻挡层由与第一扩散阻挡层相同的材料形成。 还公开了制造半导体器件的方法。

公开(公告)号：US06586842B1

公开(公告)日：2003-07-01

申请号：US09793993

申请日：2001-02-28

申请人： Lu You ,  Fei Wang ,  Christy Woo

发明人： Lu You ,  Fei Wang ,  Christy Woo

IPC分类号： H01L2352

CPC分类号： H01L21/76831 ,  H01L21/76804 ,  H01L21/76813 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a first metallization layer, a first diffusion barrier layer, a second etch stop layer, a first dielectric layer, a first etch stop layer, a second dielectric layer, a trench extending through the second dielectric layer and the first etch stop layer, and a via extending through the first dielectric layer, the second etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization layer. The second etch stop layer is disposed over and spaced from the first diffusion barrier layer, and the first dielectric layer is disposed over the second etch stop layer. The via can also have rounded corners. A third etch stop layer can also be disposed between the first diffusion barrier layer and the second etch stop layer. A sidewall diffusion barrier layer can be disposed on sidewalls of the via and trench, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. A method of manufacturing the semiconductor device is also disclosed.

摘要翻译： 半导体器件包括第一金属化层，第一扩散阻挡层，第二蚀刻停止层，第一介电层，第一蚀刻停止层，第二介电层，延伸穿过第二介电层的沟槽和第一蚀刻停止层 层，以及延伸穿过第一介电层，第二蚀刻停止层和第一扩散阻挡层的通孔。 第一扩散阻挡层设置在第一金属化层上。 第二蚀刻停止层设置在第一扩散阻挡层之上并与第一扩散阻挡层隔开，并且第一介电层设置在第二蚀刻停止层上。 通孔也可以有圆角。 第三蚀刻停止层也可以设置在第一扩散阻挡层和第二蚀刻停止层之间。 侧壁扩散阻挡层可以设置在通孔和沟槽的侧壁上，并且侧壁扩散阻挡层由与第一扩散阻挡层相同的材料形成。 还公开了制造半导体器件的方法。

公开(公告)号：US06577009B1

公开(公告)日：2003-06-10

申请号：US09776718

申请日：2001-02-06

申请人： Lu You ,  Fei Wang ,  Minh Van Ngo

发明人： Lu You ,  Fei Wang ,  Minh Van Ngo

IPC分类号： H01L2352

CPC分类号： H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a first metallization layer, a first diffusion barrier layer, a first etch stop layer, a dielectric layer and a via extending through the dielectric layer, the first etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization layer. The first etch stop layer is disposed over the first diffusion barrier layer, and the dielectric layer is disposed over the first etch stop layer. The via can also have rounded corners. A sidewall diffusion barrier layer can be disposed on sidewalls of the via, and the sidewall diffusion barrier layer is formed from the same material.as the first diffusion barrier layer. The first diffusion barrier layer can be formed from silicon carbide. A method of manufacturing the semiconductor device is also disclosed.

摘要翻译： 半导体器件包括第一金属化层，第一扩散阻挡层，第一蚀刻停止层，介电层和延伸穿过介电层的通孔，第一蚀刻停止层和第一扩散阻挡层。 第一扩散阻挡层设置在第一金属化层上。 第一蚀刻停止层设置在第一扩散阻挡层上，并且电介质层设置在第一蚀刻停止层上。 通孔也可以有圆角。 侧壁扩散阻挡层可以设置在通孔的侧壁上，并且侧壁扩散阻挡层由第一扩散阻挡层中的相同材料形成。 第一扩散阻挡层可以由碳化硅形成。 还公开了制造半导体器件的方法。

公开(公告)号：US06465361B1

公开(公告)日：2002-10-15

申请号：US09785444

申请日：2001-02-20

申请人： Lu You ,  Steve Avanzino ,  Fei Wang

发明人： Lu You ,  Steve Avanzino ,  Fei Wang

IPC分类号： H01L21302

CPC分类号： H01L21/76802

摘要： A process for manufacturing a semiconductor device includes forming a first metallization level, forming a first etch stop layer, forming a low-k dielectric layer, forming a cap layer, depositing a resist, forming an opening; removing the resist, curing the dielectric material, etching the first etch stop layer, and filing the opening with metal. The first etch stop layer is formed over the first metallization level, and the low-k dielectric layer material is formed over the first etch stop layer. The cap layer is formed over the low-k dielectric layer material, and the resist is formed over the dielectric layer. Etching is used to form the opening. The resist is removed with an O2 stripping process. Curing of the dielectric material forms a dielectric layer and occurs after the resist is removed.

摘要翻译： 制造半导体器件的工艺包括形成第一金属化层，形成第一蚀刻停止层，形成低k电介质层，形成覆盖层，沉积抗蚀剂，形成开口; 去除抗蚀剂，固化电介质材料，蚀刻第一蚀刻停止层，并用金属填充开口。 在第一金属化层上形成第一蚀刻停止层，并且在第一蚀刻停止层上形成低k电介质层材料。 盖层形成在低k电介质层材料上，并且抗蚀剂形成在介电层上。 蚀刻用于形成开口。 用O2剥离工艺除去抗蚀剂。 电介质材料的固化形成电介质层，并且在抗蚀剂除去之后发生。

公开(公告)号：US06939793B1

公开(公告)日：2005-09-06

申请号：US10422784

申请日：2003-04-25

申请人： Lu You ,  Fei Wang ,  Christy Woo

发明人： Lu You ,  Fei Wang ,  Christy Woo

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/4763

CPC分类号： H01L21/76831 ,  H01L21/76804 ,  H01L21/76813 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a first metallization layer, a first diffusion barrier layer, a second etch stop layer, a first dielectric layer, a first etch stop layer, a second dielectric layer, a trench extending through the second dielectric layer and the first etch stop layer, and a via extending through the first dielectric layer, the second etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization layer. The second etch stop layer is disposed over and spaced from the first diffusion barrier layer, and the first dielectric layer is disposed over the second etch stop layer. The via can also have rounded corners. A third etch stop layer can also be disposed between the first diffusion barrier layer and the second etch stop layer. A sidewall diffusion barrier layer can be disposed on sidewalls of the via and trench, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. A method of manufacturing the semiconductor device is also disclosed.

摘要翻译： 半导体器件包括第一金属化层，第一扩散阻挡层，第二蚀刻停止层，第一介电层，第一蚀刻停止层，第二介电层，延伸穿过第二介电层的沟槽和第一蚀刻停止层 层，以及延伸穿过第一介电层，第二蚀刻停止层和第一扩散阻挡层的通孔。 第一扩散阻挡层设置在第一金属化层上。 第二蚀刻停止层设置在第一扩散阻挡层之上并与第一扩散阻挡层隔开，并且第一介电层设置在第二蚀刻停止层上。 通孔也可以有圆角。 第三蚀刻停止层也可以设置在第一扩散阻挡层和第二蚀刻停止层之间。 侧壁扩散阻挡层可以设置在通孔和沟槽的侧壁上，并且侧壁扩散阻挡层由与第一扩散阻挡层相同的材料形成。 还公开了制造半导体器件的方法。

公开(公告)号：US06756300B1

公开(公告)日：2004-06-29

申请号：US10324259

申请日：2002-12-18

申请人： Fei Wang ,  Jerry Cheng ,  Lynne A. Okada ,  Minh Quoc Tran ,  Lu You

发明人： Fei Wang ,  Jerry Cheng ,  Lynne A. Okada ,  Minh Quoc Tran ,  Lu You

IPC分类号： H01L214763

CPC分类号： H01L21/76811 ,  H01L21/76813

摘要： For forming a dual damascene opening within a dielectric material, a via mask material and a trench mask material are formed over the dielectric material. A trench opening is formed through the trench mask material, and a via opening is formed through a via mask patterning material disposed over the via and trench mask materials. The via and trench mask materials exposed through the via opening of the via mask patterning material are etched away, and the via mask patterning material is etched away. A portion of the dielectric material exposed through the via opening is etched down to the underlying interconnect structure, and a portion of the dielectric material exposed through the trench opening is etched, to form the dual damascene opening.

摘要翻译： 为了在介电材料内形成双镶嵌开口，在电介质材料上形成通孔掩模材料和沟槽掩模材料。 通过沟槽掩模材料形成沟槽开口，并且通过布置在通孔和沟槽掩模材料上方的通孔掩模图案形成材料形成通孔开口。 通过通孔掩模图形材料的通路孔露出的通孔和沟槽掩模材料被蚀刻掉，并且通孔掩模图案材料被蚀刻掉。 通过通孔开口暴露的介电材料的一部分被蚀刻到下面的互连结构上，并且蚀刻通过沟槽开口露出的电介质材料的一部分，以形成双镶嵌开口。