公开(公告)号：US20230215481A1

公开(公告)日：2023-07-06

申请号：US17568158

申请日：2022-01-04

Applicant: Ferroelectric Memory GmbH

Inventor： Johannes Ocker ,  Foroozan Koushan

IPC: G11C11/22 ,  H01L27/11507

CPC classification number: G11C11/2275 ,  H01L27/11507 ,  G11C11/221 ,  G11C11/2273

Abstract: Various aspects relate to a method of manufacturing a memory cell, the method including: forming a memory cell, wherein the memory cell comprises a spontaneously-polarizable memory element, wherein the spontaneously-polarizable memory element is in an as formed condition; and carrying out a preconditioning operation of the spontaneously-polarizable memory element to bring the spontaneously-polarizable memory element from the as formed condition into an operable condition to allow for a writing of the memory cell after the preconditioning operation is carried out.

公开(公告)号：US20220122995A1

公开(公告)日：2022-04-21

申请号：US17072077

申请日：2020-10-16

Applicant: Ferroelectric Memory GmbH

Inventor： Johannes Ocker ,  Stefan Ferdinand Müller

IPC: H01L27/1159 ,  H01L49/02 ,  H01L29/78 ,  H01L29/51 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

Abstract: According to various aspects, a memory cell is provided, the memory cell including: a capacitive memory structure; and a field-effect transistor structure including a gate isolation, wherein the capacitive memory structure and the field-effect transistor structure are coupled with one another to form a capacitive voltage divider, wherein the gate isolation includes at least one gate isolation layer, the at least one gate isolation layer including a material having a dielectric constant greater than 4, and wherein a thickness of the at least one gate isolation layer is in the range from 3 nm to 10 nm.

公开(公告)号：US20190130956A1

公开(公告)日：2019-05-02

申请号：US15796154

申请日：2017-10-27

Applicant: Ferroelectric Memory GmbH

Inventor： Stefan Ferdinand Müller ,  Marko Noack ,  Johannes Ocker ,  Rolf Jähne

IPC: G11C11/22 ,  G11C16/04 ,  H01L27/11585 ,  H01L29/78 ,  H01L29/06 ,  H01L29/51

CPC classification number: G11C11/2275 ,  G11C11/221 ,  G11C11/223 ,  G11C11/2273 ,  G11C16/04 ,  H01L27/11507 ,  H01L27/11585 ,  H01L27/1159 ,  H01L29/0673 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/76 ,  H01L29/78391

Abstract: According to various embodiments, a memory cell may include: a field-effect transistor structure comprising a channel region and a gate structure disposed at the channel region, the gate structure comprising a gate electrode structure and a gate isolation structure disposed between the gate electrode structure and the channel region; and a memory structure comprising a first electrode structure, a second electrode structure, and at least one remanent-polarizable layer disposed between the first electrode structure and the second electrode structure; wherein the first electrode structure of the memory structure is electrically conductively connected to the gate electrode structure of the field-effect transistor structure.

公开(公告)号：US20230284454A1

公开(公告)日：2023-09-07

申请号：US18117357

申请日：2023-03-03

Applicant: Ferroelectric Memory GmbH

Inventor： Johannes Ocker ,  Stefan Ferdinand Müller ,  Patrick Polakowski

IPC: H10B51/30 ,  H01L29/78 ,  H01L29/51 ,  H01L29/417 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H10B51/30 ,  H01L28/60 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7851 ,  H01L29/78696

Abstract: A memory cell includes a capacitive memory structure comprising a first electrode; a field-effect transistor structure comprising a gate electrode; one or more insulator layers; one or more source/drain contact structures embedded in the one or more insulator layers to electrically contact the field-effect transistor structure; and a connection structure embedded in at least one of the one or more insulator layers; and one or more electrically insulating structures in addition to the one or more insulator layers configured to prevent a leakage current-induced charging of the first electrode, the gate electrode, and the connection structure, wherein the one or more electrically insulating structures comprise: a memory charge-prevention layer disposed between the first electrode of the capacitive memory structure and at least one of the one or more insulator layers, the memory charge-prevention layer laterally surrounding the first electrode of the capacitive memory structure.

公开(公告)号：US11682461B2

公开(公告)日：2023-06-20

申请号：US17691821

申请日：2022-03-10

Applicant: Ferroelectric Memory GmbH

Inventor： Menno Mennenga ,  Johannes Ocker

IPC: G11C16/24 ,  G11C16/30 ,  G11C16/08

CPC classification number: G11C16/24 ,  G11C16/08 ,  G11C16/30

Abstract: A memory cell arrangement is provided that may include: a plurality of first control lines; a plurality of second control lines; a plurality of third control lines; each of a plurality of memory cell sets includes memory cells and is assigned to a corresponding one of the plurality of first control lines and includes at least a first memory cell subset addressable via the corresponding first control line, a corresponding one of the plurality of second control lines, and the plurality of third control lines, and at least a second memory cell subset addressable via the corresponding first control line, the plurality of second control lines, and a corresponding one of the plurality of third control lines. The corresponding one of the plurality of third control lines addresses the second memory cell subset of each memory cell set of the plurality of memory cell sets.

公开(公告)号：US11527551B2

公开(公告)日：2022-12-13

申请号：US17085100

申请日：2020-10-30

Applicant: Ferroelectric Memory GmbH

Inventor： Johannes Ocker

IPC: H01L27/11 ,  H01L27/1159 ,  G11C11/22 ,  H01L27/11587

Abstract: A memory cell arrangement may include: a first memory cell including a first field-effect transistor structure, a first capacitive memory structure coupled to a gate of the first field-effect transistor structure, and a first capacitive lever structure coupled to the gate of the first field-effect transistor structure, and wherein a second memory cell of the plurality of memory cells includes a second field-effect transistor structure, a second capacitive memory structure coupled to a gate of the second field-effect transistor structure, and a second capacitive lever structure coupled to the gate of the second field-effect transistor structure; wherein at least one of the first capacitive memory structure and/or the second capacitive memory structure is disposed in a memory structure region between the first capacitive lever structure and the second capacitive lever structure.

公开(公告)号：US20220199166A1

公开(公告)日：2022-06-23

申请号：US17691821

申请日：2022-03-10

Applicant: Ferroelectric Memory GmbH

Inventor： Menno Mennenga ,  Johannes Ocker

IPC: G11C16/24 ,  G11C16/30 ,  G11C16/08

Abstract: A memory cell arrangement is provided that may include: a plurality of first control lines; a plurality of second control lines; a plurality of third control lines; each of a plurality of memory cell sets includes memory cells and is assigned to a corresponding one of the plurality of first control lines and includes at least a first memory cell subset addressable via the corresponding first control line, a corresponding one of the plurality of second control lines, and the plurality of third control lines, and at least a second memory cell subset addressable via the corresponding first control line, the plurality of second control lines, and a corresponding one of the plurality of third control lines. The corresponding one of the plurality of third control lines addresses the second memory cell subset of each memory cell set of the plurality of memory cell sets.

公开(公告)号：US20220020776A1

公开(公告)日：2022-01-20

申请号：US17356953

申请日：2021-06-24

Applicant: Ferroelectric Memory GmbH

Inventor： Menno Mennenga ,  Johannes Ocker

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L27/11504 ,  G11C11/22 ,  H01L27/11514

Abstract: A memory cell arrangement is provided that may include: a plurality of electrode layers, wherein each of the plurality of electrode layers comprises a plurality of through holes, each of the plurality of through holes extending from a first surface to a second surface of a respective electrode layer; a plurality of electrode pillars, wherein each of the plurality of electrode pillars comprises a plurality of electrode portions, wherein each of the plurality of electrode portions is disposed within a corresponding one of the plurality of through holes; wherein the respective electrode layer and a respective electrode portion of the plurality of electrode portions form a first electrode and a second electrode of a capacitor and wherein at least one memory material portion is disposed in each of the plurality of through holes in a gap between the respective electrode layer and the respective electrode portion.

公开(公告)号：US20210090662A1

公开(公告)日：2021-03-25

申请号：US16929685

申请日：2020-07-15

Applicant: Ferroelectric Memory GmbH

Inventor： Menno Mennenga ,  Johannes Ocker

IPC: G11C16/24 ,  G11C16/08 ,  G11C16/30

Abstract: A memory cell arrangement is provided that may include: a plurality of first control lines; a plurality of second control lines; a plurality of third control lines; each of a plurality of memory cell sets includes memory cells and is assigned to a corresponding one of the plurality of first control lines and includes at least a first memory cell subset addressable via the corresponding first control line, a corresponding one of the plurality of second control lines, and the plurality of third control lines, and at least a second memory cell subset addressable via the corresponding first control line, the plurality of second control lines, and a corresponding one of the plurality of third control lines. The corresponding one of the plurality of third control lines addresses the second memory cell subset of each memory cell set of the plurality of memory cell sets.

公开(公告)号：US11996131B2

公开(公告)日：2024-05-28

申请号：US17568158

申请日：2022-01-04

Applicant: Ferroelectric Memory GmbH

Inventor： Johannes Ocker ,  Foroozan Koushan

IPC: G11C11/22 ,  H10B53/30

CPC classification number: G11C11/2275 ,  G11C11/221 ,  H10B53/30 ,  G11C11/2273

Abstract: Various aspects relate to a method of manufacturing a memory cell, the method including: forming a memory cell, wherein the memory cell comprises a spontaneously-polarizable memory element, wherein the spontaneously-polarizable memory element is in an as formed condition; and carrying out a preconditioning operation of the spontaneously-polarizable memory element to bring the spontaneously-polarizable memory element from the as formed condition into an operable condition to allow for a writing of the memory cell after the preconditioning operation is carried out.