公开(公告)号：US20230284454A1

公开(公告)日：2023-09-07

申请号：US18117357

申请日：2023-03-03

Applicant: Ferroelectric Memory GmbH

Inventor： Johannes Ocker ,  Stefan Ferdinand Müller ,  Patrick Polakowski

IPC: H10B51/30 ,  H01L29/78 ,  H01L29/51 ,  H01L29/417 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H10B51/30 ,  H01L28/60 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7851 ,  H01L29/78696

Abstract: A memory cell includes a capacitive memory structure comprising a first electrode; a field-effect transistor structure comprising a gate electrode; one or more insulator layers; one or more source/drain contact structures embedded in the one or more insulator layers to electrically contact the field-effect transistor structure; and a connection structure embedded in at least one of the one or more insulator layers; and one or more electrically insulating structures in addition to the one or more insulator layers configured to prevent a leakage current-induced charging of the first electrode, the gate electrode, and the connection structure, wherein the one or more electrically insulating structures comprise: a memory charge-prevention layer disposed between the first electrode of the capacitive memory structure and at least one of the one or more insulator layers, the memory charge-prevention layer laterally surrounding the first electrode of the capacitive memory structure.

公开(公告)号：US20220376114A1

公开(公告)日：2022-11-24

申请号：US17749111

申请日：2022-05-19

Applicant: Ferroelectric Memory GmbH

Inventor： Stefan Ferdinand Müller

IPC: H01L29/78 ,  H01L27/1159 ,  H01L29/423

Abstract: Various aspects relate to a memory cell including: a field-effect transistor structure, the field-effect transistor structure including a gate structure to control a current flow in a channel, the gate structure including a gate isolation and a floating gate, wherein at least a part of the gate structure extends from a surface of a semiconductor layer into the semiconductor layer; and a capacitive memory structure, the capacitive memory structure including at least two electrodes and a spontaneously polarizable layer disposed between the at least two electrodes, wherein one of the at least two electrodes is in direct physical contact with the floating gate of the field-effect transistor structure, and wherein the spontaneously polarizable layer is disposed over the surface of the semiconductor layer.

公开(公告)号：US20220122995A1

公开(公告)日：2022-04-21

申请号：US17072077

申请日：2020-10-16

Applicant: Ferroelectric Memory GmbH

Inventor： Johannes Ocker ,  Stefan Ferdinand Müller

IPC: H01L27/1159 ,  H01L49/02 ,  H01L29/78 ,  H01L29/51 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

Abstract: According to various aspects, a memory cell is provided, the memory cell including: a capacitive memory structure; and a field-effect transistor structure including a gate isolation, wherein the capacitive memory structure and the field-effect transistor structure are coupled with one another to form a capacitive voltage divider, wherein the gate isolation includes at least one gate isolation layer, the at least one gate isolation layer including a material having a dielectric constant greater than 4, and wherein a thickness of the at least one gate isolation layer is in the range from 3 nm to 10 nm.

公开(公告)号：US20190130956A1

公开(公告)日：2019-05-02

申请号：US15796154

申请日：2017-10-27

Applicant: Ferroelectric Memory GmbH

Inventor： Stefan Ferdinand Müller ,  Marko Noack ,  Johannes Ocker ,  Rolf Jähne

IPC: G11C11/22 ,  G11C16/04 ,  H01L27/11585 ,  H01L29/78 ,  H01L29/06 ,  H01L29/51

CPC classification number: G11C11/2275 ,  G11C11/221 ,  G11C11/223 ,  G11C11/2273 ,  G11C16/04 ,  H01L27/11507 ,  H01L27/11585 ,  H01L27/1159 ,  H01L29/0673 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/76 ,  H01L29/78391

Abstract: According to various embodiments, a memory cell may include: a field-effect transistor structure comprising a channel region and a gate structure disposed at the channel region, the gate structure comprising a gate electrode structure and a gate isolation structure disposed between the gate electrode structure and the channel region; and a memory structure comprising a first electrode structure, a second electrode structure, and at least one remanent-polarizable layer disposed between the first electrode structure and the second electrode structure; wherein the first electrode structure of the memory structure is electrically conductively connected to the gate electrode structure of the field-effect transistor structure.

公开(公告)号：US11950430B2

公开(公告)日：2024-04-02

申请号：US17085141

申请日：2020-10-30

Applicant: Ferroelectric Memory GmbH

Inventor： Stefan Ferdinand Müller ,  Patrick Polakowski

IPC: H10B53/30 ,  H01L49/02

CPC classification number: H10B53/30 ,  H01L28/56 ,  H01L28/57 ,  H01L28/65 ,  H01L28/84

Abstract: According to various aspects, a memory cell is provided, the memory cell including: a first electrode; a second electrode; and a memory structure disposed between the first electrode and the second electrode, the first electrode, the second electrode, and the memory structure forming a memory capacitor, wherein at least one of the first electrode or the second electrode includes: a first electrode layer including a first material having a first microstructure; a functional layer in direct contact with the first electrode layer; and a second electrode layer in direct contact with the functional layer, the second electrode layer including a second material having a second microstructure different from the first microstructure.

公开(公告)号：US20220139934A1

公开(公告)日：2022-05-05

申请号：US17085449

申请日：2020-10-30

Applicant: Ferroelectric Memory GmbH

Inventor： Stefan Ferdinand Müller

IPC: H01L27/1159 ,  H01L49/02 ,  H01L29/51 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

Abstract: According to various aspects a memory cell is provided, the memory cell including: a first electrode; a second electrode; and a memory layer disposed between the first electrode and the second electrode, wherein the memory layer includes a first memory portion having a first concentration of oxygen vacancies and a second memory portion having a second concentration of oxygen vacancies different from the first concentration of oxygen vacancies.

公开(公告)号：US20230223066A1

公开(公告)日：2023-07-13

申请号：US17571074

申请日：2022-01-07

Applicant: Ferroelectric Memory GmbH

Inventor： Stefan Ferdinand Müller

IPC: G11C11/22 ,  H01L27/11507 ,  H01L27/11585 ,  H01L29/78 ,  H01L29/66

CPC classification number: G11C11/2275 ,  G11C11/223 ,  G11C11/2273 ,  H01L27/11507 ,  H01L27/11585 ,  H01L29/66795 ,  H01L29/78391

Abstract: Various aspects relate to a memory cell including a field-effect transistor structure and a capacitive memory structure, wherein the capacitive memory structure includes at least one spontaneously polarizable memory element, and wherein the field-effect transistor structure includes a source region, a drain region, a channel region extending between the source region and the drain region, and a gate structure disposed at the channel region, wherein the gate structure of the field-effect transistor structure substantially overlaps the source region of the field-effect transistor structure and/or the drain region of the field-effect transistor structure.

公开(公告)号：US20230189532A1

公开(公告)日：2023-06-15

申请号：US17548896

申请日：2021-12-13

Applicant: Ferroelectric Memory GmbH

Inventor： Stefan Ferdinand Müller

IPC: H01L27/11507

CPC classification number: H01L27/11507

Abstract: Various aspects relate to a memory cell including: a thermally insulating layer disposed over one or more metallization layers of a metallization; an embedding structure disposed over the thermally insulating layer; and a spontaneously polarizable capacitor structure disposed at least partially within the embedding structure, wherein the spontaneously polarizable capacitor structure comprises a spontaneously polarizable memory element; wherein the thermally insulating layer is configured as a heat barrier to reduce a heat transfer through the embedding structure into the one or more metallization layers.

公开(公告)号：US11443792B1

公开(公告)日：2022-09-13

申请号：US17400411

申请日：2021-08-12

Applicant: Ferroelectric Memory GmbH

Inventor： Rashid Iqbal ,  Stefano Sivero ,  Stefan Ferdinand Müller

IPC: G11C11/22 ,  H01L27/11509 ,  H01L29/78 ,  H01L29/51

Abstract: Various aspects relate to a memory cell including: a field-effect transistor memory structure, wherein a source/drain current through the field-effect transistor memory structure is a function of a gate voltage supplied to a gate of the field-effect transistor memory structure and a memory state in which the field-effect transistor memory structure is residing in; and an access device coupled to the gate of the field-effect transistor memory structure, wherein the access device is configured to control a voltage present at the gate of the field-effect transistor memory structure.

公开(公告)号：US20220139937A1

公开(公告)日：2022-05-05

申请号：US17085141

申请日：2020-10-30

Applicant: Ferroelectric Memory GmbH

Inventor： Stefan Ferdinand Müller ,  Patrick Polakowski

IPC: H01L27/11507 ,  H01L49/02

Abstract: According to various aspects, a memory cell is provided, the memory cell including: a first electrode; a second electrode; and a memory structure disposed between the first electrode and the second electrode, the first electrode, the second electrode, and the memory structure forming a memory capacitor, wherein at least one of the first electrode or the second electrode includes: a first electrode layer including a first material having a first microstructure; a functional layer in direct contact with the first electrode layer; and a second electrode layer in direct contact with the functional layer, the second electrode layer including a second material having a second microstructure different from the first microstructure.