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    Integrated differential pressure sensor and manufacturing process thereof
    2.
    发明申请
    Integrated differential pressure sensor and manufacturing process thereof 有权
    集成差压传感器及其制造工艺

    公开(公告)号：US20060260408A1

    公开(公告)日：2006-11-23

    申请号：US11417683

    申请日：2006-05-04

    申请人： Flavio Villa ,  Pietro Corona ,  Gabriele Barlocchi ,  Lorenzo Baldo

    发明人： Flavio Villa ,  Pietro Corona ,  Gabriele Barlocchi ,  Lorenzo Baldo

    IPC分类号： B05D5/12 ,  G01L7/08

    CPC分类号： G01L9/0045 ,  G01L13/025

    摘要： A process for manufacturing an integrated differential pressure sensor includes forming, in a monolithic body of semiconductor material having a first face and a second face, a cavity extending at a distance from the first face and delimiting therewith a flexible membrane, forming an access passage in fluid communication with the cavity, and forming, in the flexible membrane, at least one transduction element configured so as to convert a deformation of the flexible membrane into electrical signals. The cavity is formed in a position set at a distance from the second face and delimits, together with the second face, a portion of the monolithic body. In order to form the access passage, the monolithic body is etched so as to form an access trench extending through it.

    摘要翻译： 一种用于制造集成差压传感器的方法，包括在具有第一面和第二面的半导体材料的整体中形成一个与第一面相距一定距离的空腔，并将其限定在柔性膜上，形成入口通道 与空腔流体连通，以及在柔性膜中形成至少一个换能元件，其构造成将柔性膜的变形转换为电信号。 空腔形成在距第二面一定距离处的位置，并与第二面一起界定整体式的一部分。 为了形成进入通道，对整体式主体进行蚀刻以便形成延伸通过其的通道沟槽。

    Process for manufacturing thick suspended structures of semiconductor material
    5.
    发明申请
    Process for manufacturing thick suspended structures of semiconductor material 有权
    用于制造半导体材料的厚悬浮结构的方法

    公开(公告)号：US20070126071A1

    公开(公告)日：2007-06-07

    申请号：US11541376

    申请日：2006-09-27

    申请人： Pietro Corona ,  Flavio Villa ,  Gabriele Barlocchi

    发明人： Pietro Corona ,  Flavio Villa ,  Gabriele Barlocchi

    IPC分类号： H01L29/84 ,  H01L21/00

    CPC分类号： B81C1/00158 ,  B81B2201/025 ,  B81B2203/0109 ,  B81B2203/0315

    摘要： A process for manufacturing a suspended structure of semiconductor material envisages the steps of: providing a monolithic body of semiconductor material having a front face; forming a buried cavity within the monolithic body, extending at a distance from the front face and delimiting, with the front face, a surface region of the monolithic body, said surface region having a first thickness; carrying out a thickening thermal treatment such as to cause a migration of semiconductor material of the monolithic body towards the surface region and thus form a suspended structure above the buried cavity, the suspended structure having a second thickness greater than the first thickness. The thickening thermal treatment is an annealing treatment.

    摘要翻译： 制造半导体材料的悬浮结构的方法设想的步骤：提供具有正面的半导体材料的整体; 在所述整体式主体内形成掩埋空腔，所述掩埋腔在所述前表面的一定距离处延伸并且与所述前表面一起界定所述整体式主体的表面区域，所述表面区域具有第一厚度; 进行增稠热处理，使得整体式体的半导体材料朝向表面区域移动，从而在掩埋空腔之上形成悬浮结构，该悬浮结构的第二厚度大于第一厚度。 增稠热处理是退火处理。

    Process for manufacturing a high-quality SOI wafer
    7.
    发明申请
    Process for manufacturing a high-quality SOI wafer 有权
    用于制造高质量SOI晶片的工艺

    公开(公告)号：US20070042558A1

    公开(公告)日：2007-02-22

    申请号：US11448589

    申请日：2006-06-06

    申请人： Flavio Villa ,  Pietro Corona ,  Gabriele Barlocchi

    发明人： Flavio Villa ,  Pietro Corona ,  Gabriele Barlocchi

    IPC分类号： H01L21/8222 ,  H01L21/331

    CPC分类号： H01L21/76264 ,  H01L21/3247

    摘要： In a process for manufacturing a SOI wafer, the following steps are envisaged: forming, in a monolithic body of semiconductor material having a front face, a buried cavity, which extends at a distance from the front face and delimits, with the front face, a surface region of the monolithic body, the surface region being surrounded by a bulk region and forming a flexible membrane suspended above the buried cavity; forming, through the monolithic body, at least one access passage, which reaches the buried cavity; and filling the buried cavity uniformly with an insulating region. The surface region is continuous and formed by a single portion of semiconductor material, and the buried cavity is contained and completely insulated within the monolithic body; the step of forming at least one access passage is performed after the step of forming a buried cavity.

    摘要翻译： 在制造SOI晶片的工艺中，设想以下步骤：在具有前表面的半导体材料的整体式中，与前表面相距一定距离地延伸的掩埋腔， 所述整体体的表面区域，所述表面区域被块体区域包围并形成悬浮在所述掩埋空腔上方的柔性膜; 通过整体式的主体形成至少一个到达埋入腔的进入通道; 并且用绝缘区域均匀地填充掩埋腔。 表面区域是连续的，由半导体材料的单一部分形成，并且掩埋腔被包含并在整体体内完全绝缘; 在形成掩埋腔的步骤之后，进行形成至少一个进入通道的步骤。

    Process for forming a buried cavity in a semiconductor material wafer and a buried cavity
    8.
    发明授权
    Process for forming a buried cavity in a semiconductor material wafer and a buried cavity 有权
    在半导体材料晶片和掩埋腔中形成掩埋腔的工艺

    公开(公告)号：US06992367B2

    公开(公告)日：2006-01-31

    申请号：US10712211

    申请日：2003-11-12

    申请人： Pietro Erratico ,  Enrico Sacchi ,  Flavio Villa ,  Gabriele Barlocchi ,  Pietro Corona

    发明人： Pietro Erratico ,  Enrico Sacchi ,  Flavio Villa ,  Gabriele Barlocchi ,  Pietro Corona

    IPC分类号： H01L29/00

    CPC分类号： B81C1/00404

    摘要： The process comprises the steps of forming, on top of a semiconductor material wafer, a holed mask having a lattice structure and comprising a plurality of openings each having a substantially square shape and a side with an inclination of 45° with respect to the flat of the wafer; carrying out an anisotropic etch in TMAH of the wafer, using said holed mask, thus forming a cavity, the cross section of which has the shape of an upside-down isosceles trapezium; and carrying out a chemical vapor deposition using TEOS, thus forming a TEOS layer which completely closes the openings of the holed mask and defines a diaphragm overlying the cavity and on which a suspended integrated structure can subsequently be manufactured.

    摘要翻译： 该方法包括以下步骤：在半导体材料晶片的顶部上形成具有格子结构的孔掩模，并且包括多个开口，每个开口具有大致正方形的形状，并且相对于平面的平面倾斜45° 晶圆; 在晶片的TMAH中进行各向异性蚀刻，使用所述带孔掩模，从而形成空腔，其横截面具有倒立的等腰梯形的形状; 并且使用TEOS进行化学气相沉积，由此形成TEOS层，其完全封闭了孔罩的开口，并且限定了覆盖在空腔上的隔膜，并且随后可以制造悬浮的一体结构。

    Process for manufacturing buried channels and cavities in semiconductor material wafers
    9.
    发明授权
    Process for manufacturing buried channels and cavities in semiconductor material wafers 有权
    用于在半导体材料晶片中制造掩埋沟道和空腔的工艺

    公开(公告)号：US06376291B1

    公开(公告)日：2002-04-23

    申请号：US09558959

    申请日：2000-04-25

    申请人： Gabriele Barlocchi ,  Flavio Villa ,  Pietro Corona

    发明人： Gabriele Barlocchi ,  Flavio Villa ,  Pietro Corona

    IPC分类号： H01L21338

    CPC分类号： B81C1/00047 ,  B01L3/5027 ,  B81B2203/0315 ,  B81B2203/0338 ,  B81C2201/0177 ,  H01L21/764

    摘要： A process of forming on a monocrystalline-silicon body an etching-aid region of polycrystalline silicon; forming, on the etching-aid region a nucleus region of polycrystalline silicon surrounded by a protective structure having an opening extending as far as the etching-aid region; TMAH-etching the etching-aid region and the monocrystalline body to form a tub-shaped cavity; removing the top layer of the protective structure; and growing an epitaxial layer on the monocrystalline body and the nucleus region. The epitaxial layer, of monocrystalline type on the monocrystalline body and of polycrystalline type on the nucleus region, closes upwardly the etching opening, and the cavity is thus completely embedded in the resulting wafer.

    摘要翻译： 在单晶硅体上形成多晶硅的蚀刻助剂区域的工艺; 在所述蚀刻助剂区域上形成由保护结构包围的多晶硅的核区域，所述保护结构具有延伸到所述蚀刻助剂区域的开口; TMAH蚀刻蚀刻助剂区域和单晶体体以形成桶形空腔; 去除保护结构的顶层; 并在单晶体和核区域上生长外延层。 在单晶体上的单晶型的外延层和在核区上的多晶型的外延层向上封闭蚀刻开口，并且因此该空腔完全嵌入所得的晶片中。

    Process for manufacturing low-cost and high-quality SOI substrates
    10.
    发明授权
    Process for manufacturing low-cost and high-quality SOI substrates 有权

    公开(公告)号：US07071073B2

    公开(公告)日：2006-07-04

    申请号：US10331189

    申请日：2002-12-26

    申请人： Flavio Villa ,  Gabriele Barlocchi ,  Pietro Corona

    发明人： Flavio Villa ,  Gabriele Barlocchi ,  Pietro Corona

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76262 ,  H01L21/31662 ,  H01L21/76208

    摘要： For manufacturing an SOI substrate, the following steps are carried out: providing a wafer of semiconductor material; forming, inside the wafer, a plurality of passages forming a labyrinthine cavity and laterally delimiting a plurality of pillars of semiconductor material; and oxidizing the pillars of semiconductor material to form a buried insulating layer. For forming the labyrinthine cavity, a trench is first formed in a substrate; an epitaxial layer is grown, which closes the trench at the top; the wafer is annealed so as to deform the pillars and cause them to assume a minimum-energy handlebar-like shape, and a peripheral portion of the wafer is removed to reach the labyrinthine cavity, and side inlet openings are formed in the labyrinthine cavity. Oxidation is performed by feeding an oxidizing fluid through the side inlet openings.