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公开(公告)号：US6043943A
公开(公告)日：2000-03-28
申请号：US846782
申请日：1997-04-30
申请人： Francesco Rezzi , Giuseppe Patti
发明人： Francesco Rezzi , Giuseppe Patti
CPC分类号： G11B5/012 , G11B20/10009 , G11B5/09 , G11B2005/0016
摘要： A method and a circuit for correcting asymmetry in a response signal generated by a magneto-resistive head. The magneto-resistive head generates a response signal to transmit digital information read from a magnetic media storage device. The asymmetry is corrected in a negative feedback manner by squaring an output signal, modulating the squared output signal, and subtracting the modulated squared output signal from the response signal to generate the output signal. The circuit employs a differential amplifier as an input stage and a Gilbert multiplier circuit to square the output signal.
摘要翻译： 一种用于校正由磁阻头产生的响应信号中的不对称的方法和电路。 磁阻头产生响应信号以传送从磁性介质存储装置读取的数字信息。 通过平方输出信号，调制平方输出信号，以及从响应信号中减去经调制的平方输出信号以产生输出信号，以负反馈方式校正不对称性。 该电路采用差分放大器作为输入级和吉尔伯特乘法器电路对输出信号进行平方。
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公开(公告)号：US07595745B1
公开(公告)日：2009-09-29
申请号：US11836619
申请日：2007-08-09
IPC分类号： H03M1/00
CPC分类号： H03K3/356113
摘要： In a circuit to convert a first logic signal having a first range to a second logic signal having a second range, a switch selectively couples an output node to a first reference voltage when the output node is to be in a first state based on the control signal. A source-follower circuit having a current source establishes a second reference voltage. A logic circuit coupled to the switch and the source-follower circuit and having a logic gate selectively discharges, in accordance with the control signal, the output node to the second reference voltage when the output node is to transition from the first state to a second state.
摘要翻译： 在将具有第一范围的第一逻辑信号转换成具有第二范围的第二逻辑信号的电路中，当输出节点将基于控制的第一状态时，开关选择性地将输出节点耦合到第一参考电压 信号。 具有电流源的源极跟随器电路建立第二参考电压。 耦合到开关和源极跟随器电路并且具有逻辑门的逻辑电路在输出节点要从第一状态转变到第二状态时，根据控制信号将输出节点选择性地放电到第二参考电压 州。
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公开(公告)号：US07511649B1
公开(公告)日：2009-03-31
申请号：US11846292
申请日：2007-08-28
申请人： Francesco Rezzi , Nicola Ghittori , Giovanni Antonio Cesura , Shafiq M. Jamal , Stefano Marchesi
发明人： Francesco Rezzi , Nicola Ghittori , Giovanni Antonio Cesura , Shafiq M. Jamal , Stefano Marchesi
IPC分类号： H03M1/66
CPC分类号： H03K17/6871 , H03K3/35613
摘要： In a circuit to convert a first logic signal having a first range to a second logic signal having a second range, a first metal oxide semiconductor (MOS) transistor selectively couples an output node to a first reference voltage when the output node is to be in a first state. A second MOS transistor has a source coupled to the output node and a gate coupled to a bias voltage. A current source circuit selectively biases the second MOS transistor to act as part of a source-follower circuit when the output node is to be in a second state. Additionally, a memory circuit has an input coupled to the output node, and an output. The memory circuit is configured to temporarily store a Boolean value of the output node when the output node transitions from the first state to the second state. Further, a discharging circuit is coupled to the output node and a second reference voltage. The discharging circuit is configured to temporarily provide a discharging path between the output node and the second reference voltage when the output node is transitioning from the first state to the second state. The discharging circuit has a first input coupled to the output of the memory circuit and a second input coupled to a control signal. The control signal indicates that the output node is to transition from the first state to the second state.
摘要翻译： 在将具有第一范围的第一逻辑信号转换为具有第二范围的第二逻辑信号的电路中，当输出节点将处于该状态时，第一金属氧化物半导体（MOS）晶体管选择性地将输出节点耦合到第一参考电压 第一个状态 第二MOS晶体管具有耦合到输出节点的源极和耦合到偏置电压的栅极。 当输出节点处于第二状态时，电流源电路选择性地偏压第二MOS晶体管，以充当源跟随器电路的一部分。 另外，存储器电路具有耦合到输出节点的输入和输出。 存储器电路被配置为当输出节点从第一状态转换到第二状态时临时存储输出节点的布尔值。 此外，放电电路耦合到输出节点和第二参考电压。 放电电路被配置为当输出节点从第一状态转变到第二状态时临时提供输出节点与第二参考电压之间的放电路径。 放电电路具有耦合到存储器电路的输出的第一输入和耦合到控制信号的第二输入。 控制信号表示输出节点要从第一状态转换到第二状态。
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公开(公告)号：US07629909B1
公开(公告)日：2009-12-08
申请号：US11836628
申请日：2007-08-09
IPC分类号： H03M1/00
CPC分类号： H03K19/00361 , H03K17/162 , H03M1/742
摘要： In a circuit to convert a voltage range of a control signal, a first switch selectively couples, based on the control signal, an output node to a first reference voltage when the output node is to be in a first state. A second switch selectively establishes, based on the control signal, a second reference voltage when the output node is to be in a second state, the second state being a logical complement of the first state. A feedback control loop is coupled to the output node to maintain the second reference voltage in response to voltage fluctuation at the output node. The feedback control loop includes a current mirror and a transistor coupled to the current mirror. The transistor is controlled by feedback from the output node to modify a biasing current established by the current mirror to thereby counteract the voltage fluctuation.
摘要翻译： 在转换控制信号的电压范围的电路中，当输出节点处于第一状态时，第一开关基于控制信号将输出节点选择性地耦合到第一参考电压。 当输出节点处于第二状态时，第二开关基于控制信号选择性地建立第二参考电压，第二状态是第一状态的逻辑补码。 反馈控制回路耦合到输出节点以响应于输出节点处的电压波动来维持第二参考电压。 反馈控制回路包括电流镜和耦合到电流镜的晶体管。 晶体管通过来自输出节点的反馈来控制，以修改由电流镜所建立的偏置电流，从而抵消电压波动。
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公开(公告)号：US07609186B1
公开(公告)日：2009-10-27
申请号：US11836584
申请日：2007-08-09
IPC分类号： H03K19/094
CPC分类号： H03K19/018528
摘要： In a circuit to convert a first logic signal having a first range to a second logic signal having a second range, a first transistor selectively couples an output node to a first reference voltage when the output node is to be in a first state. A second transistor selectively discharges the output node toward a second reference voltage via a resistor when the output node is to transition from the first state to a second state, the second state being a logical complement of the first state. A source-follower circuit has a source follower output coupled to the output node and has a dynamic current source, the dynamic current source having a control input coupled to the resistor. A third transistor selectively couples the source follower output to the dynamic current source when the output node is to be in the second state.
摘要翻译： 在将具有第一范围的第一逻辑信号转换成具有第二范围的第二逻辑信号的电路中，当输出节点处于第一状态时，第一晶体管选择性地将输出节点耦合到第一参考电压。 当输出节点要从第一状态转变到第二状态时，第二晶体管通过电阻器选择性地将输出节点放电到第二参考电压，第二状态是第一状态的逻辑补码。 源跟随器电路具有耦合到输出节点并具有动态电流源的源极跟随器输出，动态电流源具有耦合到电阻器的控制输入。 当输出节点处于第二状态时，第三晶体管选择性地将源极跟随器输出耦合到动态电流源。
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公开(公告)号：US07605608B1
公开(公告)日：2009-10-20
申请号：US11836571
申请日：2007-08-09
IPC分类号： H03K19/094
CPC分类号： H03K19/018521 , H03M1/742
摘要： In a circuit to convert a first logic signal having a first range to a second logic signal having a second range, a first metal oxide semiconductor (MOS) transistor selectively couples an output node to a first reference voltage when the output node is to be in a first state. A second MOS transistor selectively discharges the output node toward a second reference voltage when the output node is to transition from the first state to a second state, the second state a logical complement of the first state. An output of a source-follower circuit, having a current source, is coupled to the output node. A third MOS transistor selectively couples the current source of the source-follower circuit to the second reference voltage when the output node is to be in the second state.
摘要翻译： 在将具有第一范围的第一逻辑信号转换为具有第二范围的第二逻辑信号的电路中，当输出节点将处于该状态时，第一金属氧化物半导体（MOS）晶体管选择性地将输出节点耦合到第一参考电压 第一个状态 当输出节点从第一状态转变到第二状态时，第二MOS晶体管选择性地将输出节点放电到第二参考电压，第二状态是第一状态的逻辑补码。 具有电流源的源跟随器电路的输出耦合到输出节点。 当输出节点处于第二状态时，第三MOS晶体管将源极跟随器电路的电流源选择性地耦合到第二参考电压。
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7.发明授权公开(公告)号：US06492918B1
公开(公告)日：2002-12-10
申请号：US09410276
申请日：1999-09-30
申请人： Francesco Rezzi , Marcus Marrow
发明人： Francesco Rezzi , Marcus Marrow
IPC分类号： H03M506
CPC分类号： H03M13/098 , G11B20/14 , G11B20/18 , H03M13/09
摘要： A code word includes a first group of data bits and includes code bits that represent a second group of data bits. One embodiment of the code word has a minimum probability of bit transitions among its bits. Another embodiment of the code word includes a parity bit. Unlike conventional codes, a code that includes such a code word can have both a high efficiency and small error propagation. Additionally, by including fewer bit transitions, a sequence of such code words causes less read noise, and thus causes fewer read errors as compared to sequences of known code words. Moreover, the code word can include a parity bit to allow improved error detection as compared to known error-detection techniques. Therefore, such a code word can significantly increase the effective write and read speeds of a disk drive.
摘要翻译： 代码字包括第一组数据位，并且包括表示第二组数据位的代码位。 代码字的一个实施例在其位之间具有最小的位转换概率。 代码字的另一实施例包括奇偶校验位。 与传统代码不同，包含这样的代码字的代码可以具有高效率和小错误传播。 另外，通过包括更少的位转换，这种码字的序列导致更少的读取噪声，并且因此与已知码字的序列相比导致更少的读取错误。 此外，与已知的错误检测技术相比，代码字可以包括奇偶校验位以允许改进的错误检测。 因此，这样的代码字可以显着增加磁盘驱动器的有效写入和读取速度。
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公开(公告)号：US07888973B1
公开(公告)日：2011-02-15
申请号：US12133119
申请日：2008-06-04
申请人： Francesco Rezzi , Antonio Liscidini
发明人： Francesco Rezzi , Antonio Liscidini
IPC分类号： H03B21/00
摘要： The present disclosure provides for a time to digital converter (TDC). The time to digital converter can include a reference ingress that receives a reference signal and passes the reference signal through multiple delay elements, a clock signal ingress that receives a clock signal and passes the clock signal through another set of delay elements, and multiple comparators, which are fewer in number than the total number of delay elements. The multiple comparators 1) receive the delayed reference and delayed clock signals and 2) output a set of comparison results for comparisons of pairs of delayed references and delayed clock signals.
摘要翻译： 本公开提供了一种时间到数字转换器（TDC）。 数字转换器的时间可以包括参考入口，其接收参考信号并通过多个延迟元件传递参考信号;时钟信号入口，其接收时钟信号并使时钟信号通过另一组延迟元件，以及多个比较器， 数量少于延迟元件总数。 多个比较器1）接收延迟的参考和延迟时钟信号，以及2）输出一组比较结果，用于比较延迟参考对和延迟时钟信号对。
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9.发明授权Parity- sensitive Viterbi detector and method for recovering information from a read signal 有权奇偶校验敏感维特比检测器和从读信号中恢复信息的方法公开(公告)号：US06662338B1
公开(公告)日：2003-12-09
申请号：US09409923
申请日：1999-09-30
申请人： Francesco Rezzi , Marcus Marrow
发明人： Francesco Rezzi , Marcus Marrow
IPC分类号： H03M1303
摘要： A Viterbi detector receives a signal that represents a sequence of values. The detector recovers the sequence from the signal by identifying surviving paths of potential sequence values and periodically eliminating the identified surviving paths having a predetermined parity. By recognizing the parity of portions of a data sequence, such a Viterbi detector more accurately recovers data from a read signal having a reduced SNR and thus allows an increase in the storage density of a disk drive's storage disk. Specifically, the Viterbi detector recovers only sequence portions having a recognized parity such as even parity and disregards sequence portions having unrecognized parities. If one encodes these sequence portions such that the disk stores them having the recognized parity, then an erroneously read word is more likely to have an unrecognized parity than it is to have the recognized parity. Therefore, by disregarding words that have unrecognized parities, the: accuracy, of such a Viterbi detector is considerably greater than the accuracy of prior Viterbi detectors, which cannot distinguish sequence portions based on parity. This greater accuracy allows the Viterbi detector to more accurately recover data from a read signal having a relatively low SNR, and thus allows the Viterbi detector to more accurately recover data from a disk having a relatively high storage density.
摘要翻译： 维特比检测器接收表示值序列的信号。 检测器通过识别潜在序列值的幸存路径并且周期性地消除具有预定奇偶校验的所识别的存活路径，从信号中恢复序列。 通过识别数据序列的部分的奇偶校验，这种维特比检测器更准确地从具有降低的SNR的读取信号中恢复数据，从而允许增加磁盘驱动器的存储盘的存储密度。 具体来说，维特比检测器仅恢复具有识别的奇偶校验的序列部分，例如偶校验，并忽略具有未被识别的奇偶校验的序列部分。 如果对这些序列部分进行编码，使得盘存储具有识别的奇偶校验，则错误读取的字更可能具有不具有识别的奇偶校验的奇偶校验。 因此，通过忽略具有未被认可的奇偶校验的单词，这样的维特比检测器的精度远远大于先前的维特比检测器的精度，其不能基于奇偶校验来区分序列部分。 这种更高的精度允许维特比检测器从具有相对低的SNR的读取信号更准确地恢复数据，并且因此允许维特比检测器更准确地从具有较高存储密度的盘中恢复数据。
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公开(公告)号：US5394112A
公开(公告)日：1995-02-28
申请号：US35329
申请日：1993-03-22
申请人： Roberto Alini , Francesco Rezzi , Gianfranco Vai , Marco Gregori
发明人： Roberto Alini , Francesco Rezzi , Gianfranco Vai , Marco Gregori
CPC分类号： H03H11/0422 , H03F1/302 , H03F3/45089 , H03F3/45484 , H03H11/54 , H03F2203/45418 , H03F2203/45564 , H03F2203/45594 , H03F2203/45622 , H03F2203/45626 , H03F2203/45628 , H03F2203/45674 , H03F2203/45702
摘要： An integrated circuit transconductor stage which suppresses the dependence on temperature and production process variables of a differential transconductor stage. A negative feedback relation is used, where the output of the transconductor stage is connected to an additional current generator (which is referenced to a precision external resistor), to a capacitor, and also to the gate of a PMOS transistor which sources current to a polarization stage, which in turn sources current to the transconductor stage, or to multiple transconductor stages.
摘要翻译： 一种集成电路跨导级，其抑制了对差分跨导级的温度和生产工艺变量的依赖。 使用负反馈关系，其中跨导级的输出连接到附加电流发生器（以精密外部电阻器为基准），连接到电容器，以及连接到PMOS晶体管的栅极，PMOS晶体管将电流源源于 偏振级，其反过来将电流输送到跨导级，或者到多个跨导级。
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