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    Wireless audio output assembly for projectors
    2.
    发明申请
    Wireless audio output assembly for projectors 失效
    投影机的无线音频输出组件

    公开(公告)号：US20060132715A1

    公开(公告)日：2006-06-22

    申请号：US11014826

    申请日：2004-12-20

    申请人： Francis Ho ,  Henry Chien ,  Yu-Chin Li ,  Wen-Hung Hsu ,  Chung-Hua Tsai ,  Minglu Chen

    发明人： Francis Ho ,  Henry Chien ,  Yu-Chin Li ,  Wen-Hung Hsu ,  Chung-Hua Tsai ,  Minglu Chen

    IPC分类号： G03B31/00

    CPC分类号： G03B21/14 ,  G03B21/54 ,  G03B31/00

    摘要： The present invention discloses an improved wireless audio output assembly for projectors, which comprises a system unit having a projector circuit therein and a projector lens disposed on the exterior of the system unit, and the system unit has a card-type wireless audio output circuit installed therein and a wireless active speaker installed on the exterior of the system unit, so that a projector can be used as a standalone device without connecting to external cables to read data from a memory card, view video images, and read audio/video signals of an optical disk. The projector can be upgraded to the user's desired wireless audio output circuit by inserting various different cards for the expansion.

    摘要翻译： 本发明公开了一种用于投影机的改进的无线音频输出组件，其包括其中具有投影仪电路的系统单元和设置在系统单元的外部的投影仪透镜，并且系统单元具有安装在卡式无线音频输出电路 其中安装在系统单元的外部的无线主动扬声器，使得投影仪可以用作独立设备而不连接到外部电缆以从存储卡读取数据，观看视频图像和读取音频/视频信号 光盘。 投影机可以通过插入各种不同的扩展卡来升级到用户所需的无线音频输出电路。

    Wireless audio output assembly for projectors
    3.
    发明授权
    Wireless audio output assembly for projectors 失效
    投影机的无线音频输出组件

    公开(公告)号：US07252383B2

    公开(公告)日：2007-08-07

    申请号：US11014826

    申请日：2004-12-20

    申请人： Francis Ho ,  Henry Chien ,  Yu-Chin Li ,  Wen-Hung Hsu ,  Chung-Hua Tsai ,  Minglu Chen

    发明人： Francis Ho ,  Henry Chien ,  Yu-Chin Li ,  Wen-Hung Hsu ,  Chung-Hua Tsai ,  Minglu Chen

    IPC分类号： G03B31/00 ,  G03B21/14 ,  G03B21/22 ,  G03B21/26 ,  H04N5/64

    CPC分类号： G03B21/14 ,  G03B21/54 ,  G03B31/00

    摘要： The present invention discloses an improved wireless audio output assembly for projectors, which comprises a system unit having a projector circuit therein and a projector lens disposed on the exterior of the system unit, and the system unit has a card-type wireless audio output circuit installed therein and a wireless active speaker installed on the exterior of the system unit, so that a projector can be used as a standalone device without connecting to external cables to read data from a memory card, view video images, and read audio/video signals of an optical disk. The projector can be upgraded to the user's desired wireless audio output circuit by inserting various different cards for the expansion.

    摘要翻译： 本发明公开了一种用于投影机的改进的无线音频输出组件，其包括其中具有投影仪电路的系统单元和设置在系统单元的外部的投影仪透镜，并且系统单元具有安装在卡式无线音频输出电路 其中安装在系统单元的外部的无线主动扬声器，使得投影仪可以用作独立设备而不连接到外部电缆以从存储卡读取数据，观看视频图像和读取音频/视频信号 光盘。 投影机可以通过插入各种不同的扩展卡来升级到用户所需的无线音频输出电路。

    NON-VOLATILE MEMORY CELL CONTAINING NANODOTS AND METHOD OF MAKING THEREOF
    5.
    发明申请
    NON-VOLATILE MEMORY CELL CONTAINING NANODOTS AND METHOD OF MAKING THEREOF 审中-公开
    含有纳米级的非挥发性记忆体及其制备方法

    公开(公告)号：US20110186799A1

    公开(公告)日：2011-08-04

    申请号：US13020054

    申请日：2011-02-03

    申请人： James Kai ,  Henry Chien ,  George Matamis

    发明人： James Kai ,  Henry Chien ,  George Matamis

    IPC分类号： H01L29/04 ,  H01L21/16 ,  H01L23/52 ,  B82Y99/00

    CPC分类号： B82Y10/00 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0009 ,  G11C2213/72 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/149

    摘要： A non-volatile memory cell includes a first electrode, a steering element, a storage element located in series with the steering element, a plurality of discrete conductive nano-features separated from each other by an insulating matrix, where the plurality of discrete nano-features are located in direct contact with the storage element, and a second electrode. An alternative non-volatile memory cell includes a first electrode, a steering element, a storage element located in series with the steering element, a plurality of discrete insulating nano-features separated from each other by a conductive matrix, where the plurality of discrete insulating nano-features are located in direct contact with the storage element, and a second electrode.

    摘要翻译： 非易失性存储单元包括第一电极，操舵元件，与转向元件串联定位的存储元件，多个离散的导电纳米特征，通过绝缘矩阵彼此分离，其中多个离散的纳米 - 特征位于与存储元件直接接触的位置，以及第二电极。 替代的非易失性存储单元包括第一电极，转向元件，与转向元件串联的存储元件，多个分立的绝缘纳米特征，其通过导电矩阵彼此分离，其中多个分立的绝缘 纳米特征位于与存储元件直接接触的位置，以及第二电极。

    Non-volatile memory with sidewall channels and raised source/drain regions
    6.
    发明授权
    Non-volatile memory with sidewall channels and raised source/drain regions 有权
    具有侧壁通道和升高的源极/漏极区域的非易失性存储器

    公开(公告)号：US07915664B2

    公开(公告)日：2011-03-29

    申请号：US12105242

    申请日：2008-04-17

    申请人： Henry Chien ,  Takashi Orimoto ,  George Matamis ,  James Kai ,  Vinod R. Purayath

    发明人： Henry Chien ,  Takashi Orimoto ,  George Matamis ,  James Kai ,  Vinod R. Purayath

    IPC分类号： H01L29/788

    CPC分类号： G11C8/10 ,  G11C8/04 ,  G11C11/5621 ,  G11C16/0483 ,  G11C19/00 ,  H01L21/28273 ,  H01L27/11521

    摘要： A non-volatile storage system in which a sidewall insulating layer of a floating gate is significantly thinner than a thickness of a bottom insulating layer, and in which raised source/drain regions are provided. During programming or erasing, tunneling occurs predominantly via the sidewall insulating layer and the raised source/drain regions instead of via the bottom insulating layer. The floating gate may have a uniform width or an inverted T shape. The raised source/drain regions may be epitaxially grown from the substrate, and may include a doped region above an undoped region so that the channel length is effectively extended from beneath the floating gate and up into the undoped regions, so that short channel effects are reduced. The ratio of the thicknesses of the sidewall insulating layer to the bottom insulating layer may be about 0.3 to 0.67.

    摘要翻译： 一种非易失性存储系统，其中浮动栅极的侧壁绝缘层比底部绝缘层的厚度明显薄，并且其中设置有凸起的源极/漏极区域。 在编程或擦除期间，隧道主要通过侧壁绝缘层和凸起的源极/漏极区域而不是通过底部绝缘层发生。 浮动门可以具有均匀的宽度或倒T形。 凸起的源极/漏极区域可以从衬底外延生长，并且可以包括在未掺杂区域上方的掺杂区域，使得沟道长度从浮置栅极下方有效地延伸并且向上延伸到未掺杂区域，使得短沟道效应为 减少 侧壁绝缘层与底部绝缘层的厚度的比例可以为约0.3至0.67。

    Non-volatile memory cells utilizing substrate trenches
    8.
    发明授权
    Non-volatile memory cells utilizing substrate trenches 有权

    公开(公告)号：US07087951B2

    公开(公告)日：2006-08-08

    申请号：US10848242

    申请日：2004-05-17

    申请人： Eliyahou Harari ,  Jack H. Yuan ,  George Samachisa ,  Henry Chien

    发明人： Eliyahou Harari ,  Jack H. Yuan ,  George Samachisa ,  Henry Chien

    IPC分类号： H01L29/76

    CPC分类号： H01L27/11521 ,  G11C16/0416 ,  H01L27/115 ,  H01L27/11553

    摘要： Several embodiments of flash EEPROM split-channel cell arrays are described that position the channels of cell select transistors along sidewalls of trenches in the substrate, thereby reducing the cell area. Select transistor gates are formed as part of the word lines and extend downward into the trenches with capacitive coupling between the trench sidewall channel portion and the select gate. In one embodiment, trenches are formed between every other floating gate along a row, the two trench sidewalls providing the select transistor channels for adjacent cells, and a common source/drain diffusion is positioned at the bottom of the trench. A third gate provides either erase or steering capabilities. In another embodiment, trenches are formed between every floating gate along a row, a source/drain diffusion extending along the bottom of the trench and upwards along one side with the opposite side of the trench being the select transistor channel for a cell. In another embodiment, select transistor gates of dual floating gate memory cells are extended into trenches or recesses in the substrate in order to lengthen the select transistor channel as the surface dimensions of the cell are being decreased. Techniques for manufacturing such flash EEPROM split-channel cell arrays are also included.

    Non-volatile memory cells utilizing substrate trenches
    9.
    发明授权
    Non-volatile memory cells utilizing substrate trenches 有权
    利用衬底沟槽的非易失性存储单元

    公开(公告)号：US06936887B2

    公开(公告)日：2005-08-30

    申请号：US09925134

    申请日：2001-08-08

    申请人： Eliyahou Harari ,  Jack H. Yuan ,  George Samachisa ,  Henry Chien

    发明人： Eliyahou Harari ,  Jack H. Yuan ,  George Samachisa ,  Henry Chien

    IPC分类号： H01L27/10 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/11521 ,  G11C16/0416 ,  H01L27/115 ,  H01L27/11553

    摘要： Several embodiments of flash EEPROM split-channel cell arrays are described that position the channels of cell select transistors along sidewalls of trenches in the substrate, thereby reducing the cell area. Select transistor gates are formed as part of the word lines and extend downward into the trenches with capacitive coupling between the trench sidewall channel portion and the select gate. In one embodiment, trenches are formed between every other floating gate along a row, the two trench sidewalls providing the select transistor channels for adjacent cells, and a common source/drain diffusion is positioned at the bottom of the trench. A third gate provides either erase or steering capabilities. In another embodiment, trenches are formed between every floating gate along a row, a source/drain diffusion extending along the bottom of the trench and upwards along one side with the opposite side of the trench being the select transistor channel for a cell. In another embodiment, select transistor gates of dual floating gate memory cells are extended into trenches or recesses in the substrate in order to lengthen the select transistor channel as the surface dimensions of the cell are being decreased. Techniques for manufacturing such flash EEPROM split-channel cell arrays are also included.

    摘要翻译： 描述了闪存EEPROM分离通道单元阵列的几个实施例，其将单元选择晶体管的通道定位在衬底中的沟槽的侧壁，从而减小单元面积。 选择晶体管栅极形成为字线的一部分，并且通过沟槽侧壁沟道部分和选择栅极之间的电容耦合向下延伸到沟槽中。 在一个实施例中，在沿着一行的每隔一个浮置栅极之间形成沟槽，两个沟槽侧壁为相邻电池提供选择晶体管沟道，并且公共源极/漏极扩散部位于沟槽的底部。 第三个门提供擦除或转向功能。 在另一个实施例中，在沿着一排的每个浮置栅极之间形成沟槽，沿沟槽的底部延伸的源极/漏极扩散器和沿着一侧的向上并且沟槽的相对侧为用于电池的选择晶体管沟道。 在另一个实施例中，双浮置栅极存储器单元的选择晶体管栅极延伸到衬底中的沟槽或凹槽中，以便随着单元的表面尺寸减小而延长选择晶体管沟道。 还包括用于制造这种快速EEPROM分离通道单元阵列的技术。

    Dense flash EEPROM cell array and peripheral supporting circuits formed in deposited field oxide with the use of spacers
    10.
    发明授权
    Dense flash EEPROM cell array and peripheral supporting circuits formed in deposited field oxide with the use of spacers 失效
    密封闪存EEPROM单元阵列和外围支撑电路，使用间隔物在沉积的场氧化物中形成

    公开(公告)号：US5654217A

    公开(公告)日：1997-08-05

    申请号：US413960

    申请日：1995-03-30

    申请人： Jack H. Yuan ,  Eliyahou Harari ,  Henry Chien ,  Gheorghe Samachisa

    发明人： Jack H. Yuan ,  Eliyahou Harari ,  Henry Chien ,  Gheorghe Samachisa

    IPC分类号： H01L21/8247 ,  H01L21/265

    CPC分类号： H01L27/11526 ,  H01L27/11534 ,  H01L27/11543 ,  Y10S438/917 ,  Y10S438/947

    摘要： Techniques of forming a flash EEPROM cell array with the size of individual cells being reduced, thereby increasing the number of cells which may be formed on a semiconductor substrate of a given size. Use of dielectric spacers in several steps of the process controls areas being etched or implanted with ions to something smaller than can be obtained by the highest resolution photolithography. Both split-channel and non-split-channel (no select transistor) types of memory cells are included. Example cells employ three polysilicon layers, having separate floating, control and erase gates. A technique of forming the memory cell gates with greater uniformity of conductivity level includes depositing undoped polysilicon and then using ion implantation to introduce the dopant. Field oxide is formed at an early stage in the process by CVD deposition and dry etching. The memory cell array and adjacent peripheral components are formed in a coordinated manner on a single integrated circuit chip.

    摘要翻译： 形成具有单个电池尺寸的快闪EEPROM单元阵列的技术被减少，从而增加可能形成在给定尺寸的半导体衬底上的电池数量。 在该过程的几个步骤中使用电介质间隔物控制正被蚀刻或注入离子的区域，使之比通过最高分辨率光刻可以获得的更小。 包括分离通道和非分离通道（无选择晶体管）类型的存储单元。 示例单元采用具有分离的浮置，控制和擦除栅极的三个多晶硅层。 形成具有较高导电性均匀性的存储单元栅极的技术包括沉积未掺杂的多晶硅，然后使用离子注入来引入掺杂剂。 通过CVD沉积和干蚀刻在该工艺的早期阶段形成场氧化物。 存储单元阵列和相邻的外围组件以协调的方式形成在单个集成电路芯片上。