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公开(公告)号：US07099789B1
公开(公告)日：2006-08-29
申请号：US10934121
申请日：2004-09-02
申请人： Franklyn Shihyu Wu , Jeffrey P. Erhardt , Paul J. Steffan , Jerry H. G. Tsiang , Shivananda S. Shetty , John J. Wang
发明人： Franklyn Shihyu Wu , Jeffrey P. Erhardt , Paul J. Steffan , Jerry H. G. Tsiang , Shivananda S. Shetty , John J. Wang
IPC分类号： G01R31/00
CPC分类号： G01R31/2894 , G01R31/2831
摘要： A method and system of processing tester information of a system under test is provided. Data of a tested characteristic of the system under test is generated. A distribution curve is extracted from the data. A signature of the distribution curve is determined, and a map of the signature on a depiction of the system under test is presented. The distribution curve also can be categorized in a plurality of bins, and bitmaps are generated for the sections in each of the plurality of bins. Systematic signatures are determined from the bitmaps in the block, and the signatures are correlated with the locations on the system under test.
摘要翻译： 提供了一种处理被测系统的测试仪信息的方法和系统。 产生被测系统的测试特性的数据。 从数据中提取分布曲线。 确定分布曲线的签名，并呈现在被测系统描述上的签名图。 分布曲线也可以被分类为多个箱，并且为多个箱中的每个箱中的区段生成位图。 从块中的位图确定系统签名，并将签名与被测系统上的位置相关联。
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2.发明授权Wafer level global bitmap characterization in integrated circuit technology development 有权晶圆级全局位图表征在集成电路技术开发中公开(公告)号：US07137085B1
公开(公告)日：2006-11-14
申请号：US10858739
申请日：2004-06-01
申请人： John J. Wang , Siu May Ho , Jeffrey P. Erhardt , Srikanth Sundararajan , David C. Newbury , Shivananda S. Shetty , Paul J. Steffan , Franklyn Shihyu Wu
发明人： John J. Wang , Siu May Ho , Jeffrey P. Erhardt , Srikanth Sundararajan , David C. Newbury , Shivananda S. Shetty , Paul J. Steffan , Franklyn Shihyu Wu
IPC分类号： G06F17/50
CPC分类号： G01R31/318314 , G01R31/31718 , G01R31/318511
摘要： A system and method for wafer level global bitmap characterization include determining chip level defect data bitmaps from a semiconductor wafer, and consolidating the chip level defect data bitmaps into a global wafer level bitmap that characterizes substantially the entire wafer failure configuration. The global wafer level bitmap is then analyzed and compared with other global wafer level bitmaps to develop correlations thereamong and develop global wafer level bitmap definitions for conducting at least one of wafer-to-wafer, boat-to-boat, and lot-to-lot process analysis based upon the global wafer level bitmap definitions.
摘要翻译： 用于晶片级全局位图表征的系统和方法包括从半导体晶片确定芯片级缺陷数据位图，以及将芯片级缺陷数据位图合并到表征基本上整个晶片故障配置的全局晶片级位图中。 然后分析全球晶圆级位图并与其他全球晶圆级位图进行比较，以开发相关性，并开发全球晶圆级位图定义，用于进行晶圆到晶片，船对船和批次位图中的至少一个， 基于全球晶圆级位图定义的批量处理分析。
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3.发明授权Method and apparatus for correlating semiconductor process data with known prior process data 有权将半导体工艺数据与已知的先前工艺数据相关联的方法和装置公开(公告)号：US07263451B1
公开(公告)日：2007-08-28
申请号：US10973181
申请日：2004-10-25
CPC分类号： G06T7/001 , G06T2207/30148
摘要： A method for correlating semiconductor process data analyzes a semiconductor device that has been treated by a process, to produce process data related to the process. The data is converted into an image pattern, and automatic image retrieval is used to identify other devices having similar images. The process data is then correlated with prior process data of the other devices having the similar images.
摘要翻译： 一种使半导体工艺数据相关的方法分析已经被处理过的半导体器件，以产生与该工艺有关的工艺数据。 数据被转换为图像图案，并且使用自动图像检索来识别具有相似图像的其他设备。 然后将过程数据与具有相似图像的其他设备的先前处理数据相关。
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公开(公告)号：US06875560B1
公开(公告)日：2005-04-05
申请号：US10632471
申请日：2003-08-01
IPC分类号： G01R31/28 , G03C5/00 , H01L23/544
CPC分类号： G01R31/2884 , G01R31/2831 , H01L22/34
摘要： A method of testing an integrated circuit is provided, which includes providing a semiconductor substrate having a semiconductor device provided thereon. A first dielectric layer is formed over the semiconductor substrate and a first channel is formed in the first dielectric layer in contact with the semiconductor device. A first contact pad mask layer is formed and a first contact pad in the first contact pad mask layer is formed in contact with the first channel. The first contact pad is used to test the first channel and the semiconductor device and the first contact pad mask layer and the first contact pad are removed.
摘要翻译： 提供一种测试集成电路的方法，其包括提供其上设置有半导体器件的半导体衬底。 在半导体衬底上形成第一电介质层，并且在与半导体器件接触的第一电介质层中形成第一沟道。 形成第一接触焊盘掩模层，并且第一接触焊盘掩模层中的第一接触焊盘形成为与第一通道接触。 第一接触焊盘用于测试第一通道，半导体器件和第一接触焊盘掩模层和第一接触焊盘被去除。
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5.发明授权公开(公告)号：US06864107B1
公开(公告)日：2005-03-08
申请号：US10459885
申请日：2003-06-11
CPC分类号： H01L22/20
摘要： A system of testing wafer process-splits in a semiconductor wafer is provided. A first test is performed on a semiconductor wafer in a plurality of locations to obtain first data. The first data is clustered into a plurality of bins to obtain process-split locations. Second tests are performed on the semiconductor wafer in the process-split locations to obtain second data. The first data and second data arc correlated to determine process-split data.
摘要翻译： 提供了一种在半导体晶片中测试晶片分离的系统。 在多个位置的半导体晶片上执行第一测试以获得第一数据。 第一数据被聚集成多个箱以获得处理分割位置。 在处理分离位置的半导体晶片上进行第二次测试以获得第二数据。 第一数据和第二数据相关联以确定处理分割数据。
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6.发明授权Method and apparatus for using clustering method to analyze semiconductor devices 有权使用聚类方法分析半导体器件的方法和装置公开(公告)号：US07197435B1
公开(公告)日：2007-03-27
申请号：US10817300
申请日：2004-04-02
IPC分类号： G06F15/00
CPC分类号： G01R31/31711
摘要： A method for analyzing a semiconductor device tests a semiconductor device to produce first and second data. A clustering method is applied to the first data, creating a clustered first data. The clustered first data is then correlated with the second data to determine analyzed data.
摘要翻译： 用于分析半导体器件的方法测试半导体器件以产生第一和第二数据。 聚类方法应用于第一个数据，创建一个聚簇的第一个数据。 然后将聚集的第一数据与第二数据相关以确定分析的数据。
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7.发明授权Method of simultaneous display of die and wafer characterization in integrated circuit technology development 有权在集成电路技术开发中同时显示晶片和晶圆表征的方法公开(公告)号：US06815233B1
公开(公告)日：2004-11-09
申请号：US10460615
申请日：2003-06-11
IPC分类号： G01R3126
CPC分类号： G01R31/311 , H01L22/20
摘要： A system for processing tester information is provided. Data is collected for a plurality of dies on a semiconductor wafer. Data and a pattern covering the semiconductor wafer are selected. Selected data are graphed in a trellis of graphs spread across the semiconductor wafer. The trellis of graphs is oriented over an outline of the semiconductor wafer.
摘要翻译： 提供了一种处理测试仪信息的系统。 针对半导体晶片上的多个管芯收集数据。 选择覆盖半导体晶片的数据和图案。 所选择的数据被绘制在跨越半导体晶片的图形格子中。 图形的格子定向在半导体晶片的轮廓上。
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8.发明授权公开(公告)号：US06766265B2
公开(公告)日：2004-07-20
申请号：US10323000
申请日：2002-12-18
IPC分类号： G01D300
CPC分类号： H01L22/20 , G06T11/206
摘要： A method for processing tester information is provided. The number of clusters of data in the tester information is determined to determine the number of data clusters. A basis is determined from the tester information to be used for plotting the data clusters. The data clusters are plotted on a plurality of trellis charts to form a trellising plot with a trellis of trellis charts.
摘要翻译： 提供了一种处理测试仪信息的方法。 确定测试仪信息中的数据簇的数量以确定数据簇的数量。 从用于绘制数据集群的测试者信息确定基础。 将数据集合绘制在多个网格图上以形成具有格状图格局的格局图。
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公开(公告)号：US07590309B1
公开(公告)日：2009-09-15
申请号：US10974381
申请日：2004-10-26
CPC分类号： G06T7/001 , G01N21/9501 , G01R31/2894 , G06T2207/30148
摘要： An image processing system provides a method for processing an image including classifying the image, comparing the image to stored images, storing the image if the image does not match one of the stored images, and storing a link to a stored image if the image matches one of the stored images.
摘要翻译： 图像处理系统提供一种处理图像的方法，包括对图像进行分类，将图像与存储的图像进行比较，如果图像不匹配所存储的图像之一，则存储图像，并且如果图像匹配则存储到存储的图像的链接 存储的图像之一。
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10.发明授权In-line voltage contrast determination of tunnel oxide weakness in integrated circuit technology development 失效集成电路技术开发中隧道氧化物薄弱的在线电压对比度测定公开(公告)号：US07101722B1
公开(公告)日：2006-09-05
申请号：US10839444
申请日：2004-05-04
IPC分类号： H01L21/00
CPC分类号： G01R31/307 , G01R31/2831 , G11C16/04 , G11C29/006 , G11C29/50 , G11C29/56 , G11C29/56008 , G11C2029/0403 , G11C2029/4002 , G11C2029/5004 , G11C2029/5602
摘要： A method for determination of tunnel oxide weakness is provided. A tunnel oxide layer is formed on a semiconductor wafer. At least one poly gate is formed on the tunnel oxide layer in a flash memory region of the semiconductor wafer. At least one poly island, which is substantially larger than the poly gate, is formed on the tunnel oxide layer in a voltage contrast cell region of the semiconductor wafer. The poly island and the tunnel oxide layer therebeneath form a voltage contrast tunnel oxide cell. A voltage contrast measurement is performed on the voltage contrast tunnel oxide cell. The voltage contrast measurement is then compared with prior such voltage contrast measurements on other such voltage contrast tunnel oxide cells. The tunnel oxide weakness of the tunnel oxide layer is then determined from the voltage contrast measurement comparisons.
摘要翻译： 提供了一种确定隧道氧化物弱化的方法。 在半导体晶片上形成隧道氧化物层。 在半导体晶片的闪存区域中的隧道氧化物层上形成至少一个多晶硅栅极。 在半导体晶片的电压对比单元区域中的隧道氧化物层上形成至少一个大于多晶硅栅极的多晶硅岛。 其上的多岛和隧道氧化物层形成电压对比隧道氧化物电池。 对电压对比度隧道氧化物电池进行电压对比度测量。 然后将电压对比度测量与其他这样的电压对比隧道氧化物电池的先前的这种电压对比度测量进行比较。 然后从电压对比度测量比较确定隧道氧化物层的隧道氧化物弱点。
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