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公开(公告)号：US20050122767A1
公开(公告)日：2005-06-09
申请号：US10727273
申请日：2003-12-03
申请人： Frederick Perner , Jonathan Jedwab , James Davis , David McIntyre , David Banks , Stewart Wyatt , Kenneth Smith
发明人： Frederick Perner , Jonathan Jedwab , James Davis , David McIntyre , David Banks , Stewart Wyatt , Kenneth Smith
IPC分类号： G11C7/04 , G11C11/00 , G11C11/02 , G11C11/15 , G11C29/00 , G11C29/02 , G11C29/04 , G11C29/44 , H01L21/8246 , H01L27/105 , H01L43/08
CPC分类号： G11C11/16 , G11C29/02 , G11C29/026 , G11C29/028
摘要： Embodiments of the present invention provide a magnetic memory. In one embodiment, the magnetic memory comprises an array of memory cells configured to provide resistive states, and a read circuit. The read circuit is configured to sense a resistance through a memory cell in the array of memory cells to obtain a sense result and categorize the sense result into one of at least three different categories comprising a middle category situated between the resistive states.
摘要翻译： 本发明的实施例提供一种磁存储器。 在一个实施例中，磁存储器包括被配置为提供电阻状态的存储器单元的阵列和读取电路。 读取电路被配置为感测通过存储器单元阵列中的存储器单元的电阻以获得感测结果，并将感测结果分类为包括位于电阻状态之间的中间类别的至少三个不同类别中的一个。
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公开(公告)号：US20050193312A1
公开(公告)日：2005-09-01
申请号：US10790360
申请日：2004-03-01
申请人： Kenneth Smith , Jonathan Jedwab , James Davis , David Banks
发明人： Kenneth Smith , Jonathan Jedwab , James Davis , David Banks
CPC分类号： H03M13/3761 , H03M13/09 , H03M13/1515 , H03M13/19 , H03M13/23 , H03M13/3707
摘要： A system for error correction coding and decoding information is disclosed. In one embodiment, the first and second encoders are each configured to encode the information, wherein the second encoder has a higher capability than the first encoder. First and second decoders are configured to recover the information, wherein the second decoder recovers the information encoded by the second encoder only if the first decoder cannot recover the information.
摘要翻译： 公开了一种用于纠错编码和解码信息的系统。 在一个实施例中，第一和第二编码器各自被配置为对信息进行编码，其中第二编码器具有比第一编码器更高的能力。 第一和第二解码器被配置为恢复信息，其中第二解码器仅在第一解码器不能恢复信息时才恢复由第二编码器编码的信息。
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3.发明申请Data storage system with error correction code and replaceable defective memory 审中-公开具有纠错码和可更换有缺陷的存储器的数据存储系统公开(公告)号：US20050120265A1
公开(公告)日：2005-06-02
申请号：US10725855
申请日：2003-12-02
申请人： Steven Pline , Kenneth Smith , Colin Stobbs , Stewart Wyatt , David Banks , Robin Takasugi , David McIntyre
发明人： Steven Pline , Kenneth Smith , Colin Stobbs , Stewart Wyatt , David Banks , Robin Takasugi , David McIntyre
CPC分类号： G11C29/76 , G06F11/1008 , G06F11/108 , G06F2211/109
摘要： Embodiments of the present invention provide a data storage and retrieval system operating on a host computer. The data storage and retrieval system comprises a sparing system configured to replace defective memory sections of a memory device with replacement memory sections of the memory device, and an error correction code system. The error correction code system is configured to encode data with an error correction code to store the data into the memory device and decode the encoded data with the error correction code to retrieve the data from the memory device.
摘要翻译： 本发明的实施例提供了在主计算机上操作的数据存储和检索系统。 数据存储和检索系统包括备用系统，其被配置为用存储器件的替换存储器部分替换存储器件的有缺陷的存储器部分，以及纠错码系统。 错误校正码系统被配置为用纠错码对数据进行编码，以将数据存储到存储器件中，并用纠错码对编码数据进行解码，以从存储器件检索数据。
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公开(公告)号：US20050007816A1
公开(公告)日：2005-01-13
申请号：US10784514
申请日：2004-02-23
CPC分类号： G11C11/15
摘要： A data storage device comprising a first memory cell string that includes at least a first magnetic random access memory (MRAM) cell coupled to a second MRAM cell and a circuit coupled to a node between the first MRAM cell and the second MRAM cell is provided. The circuit is configured to detect a voltage change at the node in response to a voltage being provided to the memory cell string and in response to a write sense current being applied across the first MRAM cell.
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公开(公告)号：US20050007823A1
公开(公告)日：2005-01-13
申请号：US10614581
申请日：2003-07-07
CPC分类号： G11C11/15
摘要： A data storage device that includes a memory cell string. The memory cell string includes a first memory cell and a second memory cell. The device also includes a circuit coupled to a node between the first memory cell and a second memory cell. The circuit is configured to detect a voltage change at the node in response to a voltage being provided to the memory cell string and the first memory cell being written to a first state.
摘要翻译： 一种包括存储单元串的数据存储装置。 存储单元串包括第一存储单元和第二存储单元。 该装置还包括耦合到第一存储单元和第二存储单元之间的节点的电路。 电路被配置为响应于提供给存储器单元串并且第一存储器单元被写入第一状态的电压来检测节点处的电压变化。
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公开(公告)号：US07266732B2
公开(公告)日：2007-09-04
申请号：US10743662
申请日：2003-12-22
IPC分类号： G06F11/00
CPC分类号： G11C11/16 , G06F11/1008 , G11C11/15 , G11C29/42 , G11C29/70 , G11C2029/0409
摘要： A memory card comprising an magnetic random access memory (MRAM) array that comprises a plurality of magnetic memory cells and a controller coupled to the MRAM array. The controller is configured to communicate with a host device, and the controller is configured perform an error correction function associated with at least one of the plurality of magnetic memory cells.
摘要翻译： 一种存储卡，其包括磁性随机存取存储器（MRAM）阵列，其包括多个磁存储器单元和耦合到MRAM阵列的控制器。 控制器被配置为与主机设备通信，并且配置控制器执行与多个磁存储器单元中的至少一个相关联的纠错功能。
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公开(公告)号：US20050135165A1
公开(公告)日：2005-06-23
申请号：US10743662
申请日：2003-12-22
CPC分类号： G11C11/16 , G06F11/1008 , G11C11/15 , G11C29/42 , G11C29/70 , G11C2029/0409
摘要： A memory card comprising an magnetic random access memory (MRAM) array that comprises a plurality of magnetic memory cells and a controller coupled to the MRAM array. The controller is configured to communicate with a host device, and the controller is configured perform an error correction function associated with at least one of the plurality of magnetic memory cells.
摘要翻译： 一种存储卡，其包括磁性随机存取存储器（MRAM）阵列，其包括多个磁存储器单元和耦合到MRAM阵列的控制器。 控制器被配置为与主机设备通信，并且配置控制器执行与多个磁存储器单元中的至少一个相关联的纠错功能。
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公开(公告)号：US20050281078A1
公开(公告)日：2005-12-22
申请号：US11211986
申请日：2005-08-25
申请人： Frederick Perner , Kenneth Smith
发明人： Frederick Perner , Kenneth Smith
IPC分类号： G11C11/15 , G11C11/00 , G11C11/14 , G11C11/16 , H01L21/8246 , H01L27/105 , H01L43/08
CPC分类号： G11C11/16
摘要： Methods and apparatuses are disclosed for communicating data on a chip. In one embodiment, the method includes: reading the data value of a memory element utilizing conductors that are electrically coupled to the memory element, and communicating the value read from the memory element to other locations on chip using write conductors that are magnetically coupled to the memory element.
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公开(公告)号：US20050102576A1
公开(公告)日：2005-05-12
申请号：US10698896
申请日：2003-10-31
申请人： Frederick Perner , Kenneth Smith
发明人： Frederick Perner , Kenneth Smith
CPC分类号： G11C29/02 , G11C29/026
摘要： A data storage device includes non-volatile memory; and a read circuit for performing multi-sample read operations on the memory during a normal mode of operation. The read circuit includes a digital counter having an output that indicates a single bit (e.g., a sign-bit). The read circuit allows an external device (e.g., a memory tester) to supply test clock pulses to an input of the digital counter during a test mode. The test clock pulses can be counted to determine a state of the digital counter.
摘要翻译： 数据存储装置包括非易失性存储器; 以及用于在正常操作模式期间对存储器执行多样本读取操作的读取电路。 读取电路包括具有指示单个位（例如，符号位）的输出的数字计数器。 读取电路允许外部设备（例如，存储器测试器）在测试模式期间将测试时钟脉冲提供给数字计数器的输入。 可以对测试时钟脉冲进行计数，以确定数字计数器的状态。
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公开(公告)号：US20050078536A1
公开(公告)日：2005-04-14
申请号：US10675740
申请日：2003-09-30
申请人： Frederick Perner , Kenneth Smith
发明人： Frederick Perner , Kenneth Smith
IPC分类号： G11C11/15 , G11C7/02 , G11C29/02 , H01L21/8246 , H01L27/105 , H01L43/08
CPC分类号： G11C29/02 , G11C7/02 , G11C11/1673 , G11C29/026 , G11C29/028 , G11C2207/2254
摘要： Embodiments of the present invention provide a resistive cross point memory. The resistive cross point memory comprises an array of memory cells and a read circuit. The read circuit is configured to sense a resistance through a memory cell in the array of memory cells to obtain a sense result and calibrate the read circuit based on the sensed result. The read circuit comprises an up/down counter that provides a calibration value to the read circuit.
摘要翻译： 本发明的实施例提供一种电阻式交叉点存储器。 电阻交叉点存储器包括存储器单元阵列和读取电路。 读取电路被配置为感测通过存储器单元阵列中的存储器单元的电阻以获得感测结果，并且基于感测结果来校准读取电路。 读取电路包括向读取电路提供校准值的向上/向下计数器。
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