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    SEMICONDUCTOR MODULE
    1.
    发明申请
    SEMICONDUCTOR MODULE 有权

    公开(公告)号：US20220415729A1

    公开(公告)日：2022-12-29

    申请号：US17825300

    申请日：2022-05-26

    申请人： FUJI ELECTRIC CO., LTD.

    发明人： Ryoichi KATO ,  Yuma MURATA ,  Naoyuki KANAI

    IPC分类号： H01L23/049 ,  H01L25/07 ,  H01L23/31 ,  H01L23/49 ,  H01L23/00

    摘要： There is provided a semiconductor module capable of preventing the peeling of a sealing resin on the side where connection sections used for the connection to semiconductor elements are arranged. A semiconductor module includes: an outer frame; sealing resins; gate signal output terminals, and partition sections laid across the outer flame to partition a space into a plurality of housing sections, in the partition sections which the gate signal output terminals with connection sections exposed are arranged. The partition sections have first surface sections on the side where the connection sections are arranged and second surface sections formed, on the side where the connection sections are not arranged, such that the peeling strength to the sealing resins is lower than that of the first surface sections.

    SEMICONDUCTOR MODULE
    3.
    发明申请
    SEMICONDUCTOR MODULE 有权

    公开(公告)号：US20210280549A1

    公开(公告)日：2021-09-09

    申请号：US17185953

    申请日：2021-02-25

    申请人： FUJI ELECTRIC CO., LTD.

    发明人： Ryoichi KATO ,  Yuma MURATA ,  Naoyuki KANAI ,  Akito NAKAGOME ,  Yoshinari IKEDA

    IPC分类号： H01L23/00 ,  H01L23/538 ,  H01L25/07

    摘要： A semiconductor module includes a first semiconductor element and a second semiconductor element each having an upper-surface electrode and a lower-surface electrode, and being connected in parallel to configure an upper arm, a first conductive layer having a U-shape in planar view, having two end portions, and having an upper surface on which the first semiconductor element and the second semiconductor element are disposed in a mirror image arrangement, a positive electrode terminal having a body part and at least two positive electrode ends branched from the body part, and a negative electrode terminal having a negative electrode end disposed between the positive electrode ends. The positive electrode ends are respectively connected to one of the two end portions of the first conductive layer.

    SEMICONDUCTOR DEVICE
    4.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240312948A1

    公开(公告)日：2024-09-19

    申请号：US18422213

    申请日：2024-01-25

    申请人： FUJI ELECTRIC CO., LTD.

    发明人： Yuichiro HINATA ,  Naoyuki KANAI

    IPC分类号： H01L23/00

    CPC分类号： H01L24/48 ,  H01L24/40 ,  H01L24/73 ,  H01L2224/40227 ,  H01L2224/48227 ,  H01L2224/73221

    摘要： A semiconductor device includes: a semiconductor chip; a bonding wire electrically connected to an electrode provided on the semiconductor chip; and a connecting substrate jointed to the electrode of the semiconductor chip, in which: a thermal expansion coefficient of the connecting substrate is equal to a thermal expansion coefficient of the bonding wire, or the thermal expansion coefficient of the connecting substrate is within a range of the thermal expansion coefficient of the bonding wire or less and a first thermal expansion coefficient or greater, a difference between the first thermal expansion coefficient and the thermal expansion coefficient of the bonding wire is a predetermined value, and the bonding wire is jointed to the connecting substrate to be electrically connected to the electrode via the connecting substrate.

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR
    5.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR 有权

    公开(公告)号：US20220415749A1

    公开(公告)日：2022-12-29

    申请号：US17825520

    申请日：2022-05-26

    申请人： FUJI ELECTRIC CO., LTD.

    发明人： Naoyuki KANAI ,  Shun OKADA ,  Ryoichi KATO

    IPC分类号： H01L23/367 ,  H01L23/485

    摘要： A semiconductor device includes a baseplate and a case which includes an external wall surrounding an internal space and a dividing wall extending in a first direction and separating the space into compartments. The dividing wall has a lower end fixed to the principal surface and includes, on a sidewall, a terrace positioned further away from the principal surface than the lower end and hanging out toward the space compared to the lower end in a second direction parallel to the principal surface and perpendicular to the first direction. A terminal's bonding part, to which a wire is bonded, is disposed on the terrace. A ratio of the wire's diameter to the bonding part's width in the first direction is set to ≤0.15, which prevents a situation where bonding power is not sufficiently applied to the bonding part during ultrasonic bonding of the wire, thus increasing the bonding strength.

    SEMICONDUCTOR MODULE
    6.
    发明申请
    SEMICONDUCTOR MODULE 有权

    公开(公告)号：US20210280555A1

    公开(公告)日：2021-09-09

    申请号：US17185931

    申请日：2021-02-25

    申请人： FUJI ELECTRIC CO., LTD.

    发明人： Yuma MURATA ,  Ryoichi KATO ,  Naoyuki KANAI ,  Akito NAKAGOME ,  Yoshinari IKEDA

    IPC分类号： H01L23/00 ,  H01L23/538 ,  H01L25/07

    摘要： A semiconductor module includes a case with a side wall in a first direction in which gate and source terminals are embodied and exposed therefrom, first and second semiconductor elements each having gate and source electrodes, gate and source relay layers positioned at a center between the first and second semiconductor elements in the first direction at a side of the semiconductor elements farther from the side wall, first gate and source wires respectively connecting the gate and source terminals to the gate and source relay layers, second gate and source wires, and third gate and source wires, respectively connecting the gate and source electrodes of the first semiconductor element, and the gate and source electrode of the second semiconductor element, to the gate and source relay layers. The first to third source wires are respectively located closer to the first to third gate wires than any other gate wires.

    SEMICONDUCTOR MODULE
    9.
    发明申请
    SEMICONDUCTOR MODULE 有权

    公开(公告)号：US20210280556A1

    公开(公告)日：2021-09-09

    申请号：US17187646

    申请日：2021-02-26

    申请人： FUJI ELECTRIC CO., LTD.

    发明人： Ryoichi KATO ,  Yuma MURATA ,  Naoyuki KANAI ,  Akito NAKAGOME ,  Yoshinari IKEDA

    IPC分类号： H01L23/00 ,  H01L25/07 ,  H01L23/498 ,  H05K1/02 ,  H05K1/14

    摘要： A semiconductor module includes an insulating substrate having a main wiring layer, positive and negative electrode terminals adjacently arranged in a first direction, a plurality of semiconductor elements forming a first column and another plurality of semiconductor elements forming a second column, each semiconductor element having gate and source electrode on an upper surface thereof, and being disposed on the main wiring layer such that corresponding ones of the gate electrodes in the first and second columns face each other in a second direction orthogonal to the first direction, a control wiring substrate between the first and second columns and having gate and source wiring layers, a gate wiring member connecting ones of the gate electrodes in the first and second columns through the gate wiring layer, and a source wiring member connecting ones of the source electrodes in the first and second columns through the source wiring layer.