公开(公告)号：US20240339434A1

公开(公告)日：2024-10-10

申请号：US18624674

申请日：2024-04-02

申请人： II-VI Delaware, Inc.

发明人： Erno TEMESI ,  Zoltan KEPIRO ,  Philippe DUPIN

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC分类号： H01L25/0655 ,  H01L24/13 ,  H01L24/40 ,  H01L24/48 ,  H01L24/73 ,  H01L25/50 ,  H01L2224/13016 ,  H01L2224/40227 ,  H01L2224/48227 ,  H01L2224/73205 ,  H01L2224/73207

摘要： This disclosure describes a power semiconductor module with at least one controlled power semiconductor bare die on an isolation substrate. The power semiconductor bare die includes a gate and a return control connection associated with pins that extend perpendicularly from the top of the power semiconductor bare die. One or more power terminals are connected to the isolation substrate.

公开(公告)号：US20240234360A9

公开(公告)日：2024-07-11

申请号：US18454994

申请日：2023-08-24

申请人： FUJI ELECTRIC CO., LTD.

发明人： Mai SAITO ,  Daiki YOSHIDA

IPC分类号： H01L23/00 ,  H01L23/31

CPC分类号： H01L24/40 ,  H01L23/3135 ,  H01L24/05 ,  H01L24/37 ,  H01L23/3735 ,  H01L24/06 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06181 ,  H01L2224/32225 ,  H01L2224/37012 ,  H01L2224/37147 ,  H01L2224/40227 ,  H01L2224/40991 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2924/13055 ,  H01L2924/13091

摘要： A semiconductor module includes a circuit board having a semiconductor element mounted thereon, a lead including a first bonding portion bonded to the semiconductor element via a bonding material and a wiring portion connected to the first bonding portion, and a sealing material that seals the semiconductor element and the lead. The first bonding portion has first and second side surfaces that face each other. The wiring portion has a bent portion connected to the first bonding portion at a side of the first bonding portion at which the first side surface is located. The bent portion is bent at a border between the first bonding portion and the bent portion in a direction away from a lower surface of the first bonding portion. The border is located between the first and second side surfaces of the first bonding portion in a plan view of the lead.

公开(公告)号：US11948911B2

公开(公告)日：2024-04-02

申请号：US17308473

申请日：2021-05-05

申请人： TONGFU MICROELECTRONICS CO., LTD.

发明人： Guoqing Yu

IPC分类号： H01L21/78 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L24/94 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3157 ,  H01L24/40 ,  H01L24/48 ,  H01L24/84 ,  H01L2224/40227 ,  H01L2224/48227 ,  H01L2224/84815 ,  H01L2224/85815

摘要： The present disclosure provides a semiconductor packaging method and a semiconductor package device. The semiconductor packaging method includes providing a chip, where the chip includes a chip substrate having a front surface and a back surface, where the front surface includes a photosensitive region; soldering pads disposed at the front surface of the chip substrate surrounding the photosensitive region; a metal part formed on a side of each soldering pad facing away from the chip substrate; and a transparent protective layer formed on the front surface of the chip substrate, where a first end of the metal part is exposed by protruding over a surface of the transparent protective layer. The method further includes electrically connecting the first end of the metal part to a circuit board using a conductive connection part, such that the chip is electrically connected to the circuit board.

公开(公告)号：US20180234093A1

公开(公告)日：2018-08-16

申请号：US15433447

申请日：2017-02-15

申请人： Infineon Technologies Austria AG

发明人： Anton Mauder ,  Martin Gruber ,  Goran Keser

IPC分类号： H03K17/687 ,  H01L23/00 ,  G06F17/50

CPC分类号： H03K17/687 ,  G01R33/09 ,  G06F17/5036 ,  H01L23/552 ,  H01L23/62 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/37011 ,  H01L2224/40227 ,  H01L2224/45014 ,  H01L2224/48227 ,  H01L2224/73221 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/30107 ,  H03K17/0822 ,  H03K17/0828 ,  H03K2217/0027

摘要： A device is provided that includes a switch within a package. A first electrical connection is provided between a load terminal of the switch and first pin of the package, and a second electrical connection at least partially different from the first electrical connection is provided between the switch and a second pin of the package. The second pin is different from the first pin.

公开(公告)号：US20180190562A1

公开(公告)日：2018-07-05

申请号：US15689828

申请日：2017-08-29

申请人： STMicroelectronics (Tours) SAS ,  STMicroelectronics (Grenoble 2) SAS

发明人： Laurent Figuiere ,  Gaetan Lobascio ,  Alexandre Mas

IPC分类号： H01L23/367 ,  H01L23/373 ,  H01L23/31 ,  H01L21/304 ,  H01L21/78 ,  H01L21/56

CPC分类号： H01L23/367 ,  H01L21/3043 ,  H01L21/56 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3178 ,  H01L23/36 ,  H01L23/3672 ,  H01L23/3675 ,  H01L23/3733 ,  H01L23/3737 ,  H01L23/42 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/73 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/2741 ,  H01L2224/27848 ,  H01L2224/2929 ,  H01L2224/29324 ,  H01L2224/29347 ,  H01L2224/32245 ,  H01L2224/37012 ,  H01L2224/40227 ,  H01L2224/40499 ,  H01L2224/73253 ,  H01L2224/73255 ,  H01L2224/83365 ,  H01L2224/84365 ,  H01L2924/10158 ,  H01L2924/15311 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/07811

摘要： An electronic device includes a support plate having a mounting face. An electronic chip has a front face mounted on the mounting face of the support plate. A rear face of the electronic chip located opposite to the front face is provided with rear grooves that define, between the grooves, rear zones. A rear layer made of a heat-conducting material is spread over the rear face of the electronic chip so as to at least partly cover the rear zones and at least partially fill the rear grooves.

公开(公告)号：US20180076728A1

公开(公告)日：2018-03-15

申请号：US15704118

申请日：2017-09-14

申请人： Delta Electronics (Shanghai) CO., LTD

发明人： Shouyu HONG ,  Juan CHENG ,  Tao WANG ,  Zhenqing ZHAO

IPC分类号： H02M7/00 ,  H02M7/48 ,  G06F1/30 ,  H02J9/06 ,  H02M1/10

CPC分类号： H02M7/003 ,  G06F1/30 ,  H01L25/072 ,  H01L25/115 ,  H01L25/16 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/32225 ,  H01L2224/37147 ,  H01L2224/40227 ,  H01L2224/48227 ,  H01L2224/49111 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30107 ,  H02J9/061 ,  H02M1/10 ,  H02M7/48 ,  H05K1/025 ,  H05K1/0265 ,  H05K2201/10015 ,  H05K2201/10166 ,  H01L2924/00

摘要： The disclosure relates to a power conversion module, including: a substrate including a routing layer and an insulating layer, the routing layer including a first routing area and a second routing area; an electronic device provided on the first routing area and electrically connected to the first routing area and the second routing area, respectively; a vertical type power device provided on the second routing area and electrically connected to the second routing area; and a capacitor provided on the substrate, disposed between the electronic device and the vertical type power device, and electrically connected to the electronic device and the vertical type power device, respectively. The power conversion module is provided with all devices on the same substrate, thus cost is reduced, yield rate and reliability are improved, and parasitic inductance inside the power conversion module can be reduced.

公开(公告)号：US20180076149A1

公开(公告)日：2018-03-15

申请号：US15666534

申请日：2017-08-01

申请人： FUJI ELECTRIC CO., LTD.

发明人： Tatsuhiko ASAI

IPC分类号： H01L23/00 ,  H01L23/492 ,  H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/367

CPC分类号： H01L23/562 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/053 ,  H01L23/24 ,  H01L23/3121 ,  H01L23/367 ,  H01L23/3735 ,  H01L23/492 ,  H01L23/49811 ,  H01L23/49844 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29147 ,  H01L2224/32225 ,  H01L2224/32227 ,  H01L2224/37013 ,  H01L2224/40095 ,  H01L2224/40225 ,  H01L2224/40227 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48175 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/84447 ,  H01L2224/84801 ,  H01L2924/014 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01083 ,  H01L2924/00012

摘要： A semiconductor device including a stacked assembly. The stacked assembly includes a metal substrate, a stacked substrate mounted on the metal substrate and having an electrode pattern, a semiconductor element mounted on the stacked substrate, and a lead frame interconnection electrically connecting the semiconductor element and the electrode pattern. The lead frame interconnection includes a first bonding portion in contact with the semiconductor element, a second bonding portion in contact with the electrode pattern, and an interconnect portion connecting the first and second bonding portions. At least one of the first bonding portion and the second bonding portion is wider than the interconnect portion.

公开(公告)号：US20170271239A1

公开(公告)日：2017-09-21

申请号：US15418787

申请日：2017-01-30

申请人： FUJI ELECTRIC CO., LTD.

发明人： Akira MOROZUMI ,  Hiromichi GOHARA ,  Yoshitaka NISHIMURA

IPC分类号： H01L23/473 ,  H01L23/42 ,  H01L23/053 ,  H01L25/11 ,  H01L23/40 ,  H01L21/50

CPC分类号： H01L23/473 ,  H01L21/50 ,  H01L23/053 ,  H01L23/3121 ,  H01L23/4006 ,  H01L23/42 ,  H01L25/072 ,  H01L25/115 ,  H01L2023/4031 ,  H01L2023/4087 ,  H01L2224/37147 ,  H01L2224/40227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2924/00014

摘要： A semiconductor module is provided, including: a cooling-target device; a first cooling unit on which the cooling-target device is placed and that has a flow channel through which a refrigerant for cooling the cooling-target device flows; and a second cooling unit to which the first cooling unit is fixed and that has a flow channel coupled with the flow channel of the first cooling unit. Also, a semiconductor module manufacturing method is provided, including: placing a cooling-target device on a first cooling unit that has a flow channel through which a refrigerant for cooling the cooling-target device flows; and fixing the first cooling unit to a second cooling unit that has a flow channel coupled with the flow channel of the first cooling unit.

公开(公告)号：US09673170B2

公开(公告)日：2017-06-06

申请号：US14451868

申请日：2014-08-05

申请人： Infineon Technologies AG

发明人： Rupert Fischer ,  Peter Strobel ,  Joachim Mahler ,  Konrad Roesl ,  Alexander Heinrich

IPC分类号： H01L21/68 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H01L21/683 ,  H01L23/495 ,  H01L23/29 ,  H01L23/31

CPC分类号： H01L24/97 ,  H01L21/6835 ,  H01L23/295 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/49575 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68354 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2224/04026 ,  H01L2224/05611 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/06181 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/40227 ,  H01L2224/40247 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/8381 ,  H01L2224/8382 ,  H01L2224/83851 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2224/95001 ,  H01L2224/95091 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/84 ,  H01L2224/27 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2924/00

摘要： Methods for connecting chips to a chip carrier are disclosed. In some embodiments the method for connecting a plurality of chips to a chip carrier includes placing first chips on a transfer carrier, placing second chips on the transfer carrier, placing the transfer carrier with the first and second chips on the chip carrier and forming connections between the first chips and the chip carrier and the second chips and the chip carrier.

公开(公告)号：US09589868B2

公开(公告)日：2017-03-07

申请号：US15064750

申请日：2016-03-09

申请人： GaN Systems Inc.

发明人： Cameron McKnight-MacNeil ,  Greg P. Klowak ,  Ahmad Mizan

IPC分类号： H01L23/00 ,  H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L23/498 ,  H01L23/492 ,  H01L23/482

CPC分类号： H01L23/49503 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/4824 ,  H01L23/492 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49861 ,  H01L24/02 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/35 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/84 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/0239 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16245 ,  H01L2224/245 ,  H01L2224/291 ,  H01L2224/29139 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/352 ,  H01L2224/37012 ,  H01L2224/37013 ,  H01L2224/37147 ,  H01L2224/40227 ,  H01L2224/40245 ,  H01L2224/40475 ,  H01L2224/40499 ,  H01L2224/41051 ,  H01L2224/4118 ,  H01L2224/73203 ,  H01L2224/73263 ,  H01L2224/81132 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81447 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/8384 ,  H01L2224/84801 ,  H01L2224/84815 ,  H01L2224/8484 ,  H01L2224/92143 ,  H01L2224/97 ,  H01L2924/00015 ,  H01L2924/01014 ,  H01L2924/04642 ,  H01L2924/1033 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/17747 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2224/81 ,  H01L2224/48

摘要： Packaging solutions for large area, GaN die comprising one or more lateral GaN power transistor devices and systems are disclosed. Packaging assemblies comprise an interposer sub-assembly comprising the lateral GaN die and a leadframe. The GaN die is electrically connected to the leadframe using bump or post interconnections, silver sintering, or other low inductance interconnections. Then, attachment of the GaN die to the substrate and the electrical connections of the leadframe to contacts on the substrate are made in a single process step. The sub-assembly may be mounted in a standard power module, or alternatively on a substrate, such as a printed circuit board. For high current applications, the sub-assembly also comprises a ceramic substrate for heat dissipation. This packaging scheme provides interconnections with lower inductance and higher current capacity, simplifies fabrication, and enables improved thermal matching of components, compared with conventional wirebonded power modules.

摘要翻译： 公开了用于大面积的包括一个或多个横向GaN功率晶体管器件和系统的GaN管芯的封装解决方案。 包装组件包括包括横向GaN管芯和引线框架的插入件子组件。 GaN管芯使用凸点或柱互连，银烧结或其他低电感互连电连接到引线框架。 然后，在单个工艺步骤中制造GaN管芯到衬底的连接以及引线框架与衬底上的触点的电连接。 子组件可以安装在标准功率模块中，或者替代地安装在诸如印刷电路板的基板上。 对于高电流应用，子组件还包括用于散热的陶瓷衬底。 与传统的引线键合功率模块相比，该封装方案提供了具有较低电感和较高电流容量的互连，简化了制造，并且能够改进组件的热匹配。