公开(公告)号：US20020094677A1

公开(公告)日：2002-07-18

申请号：US10044979

申请日：2002-01-15

申请人： Fujitsu Quantum Devices Limited

发明人： Akira Furuya ,  Chikashi Anayama ,  Katsumi Sugiura ,  Kensei Nakao ,  Taro Hasegawa

IPC分类号： H01L021/44

CPC分类号： B82Y20/00 ,  H01L21/02395 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02505 ,  H01L21/02546 ,  H01L21/02576 ,  H01L21/0262 ,  H01S5/2201 ,  H01S5/2238 ,  H01S5/305 ,  H01S5/3054 ,  H01S5/34326 ,  H01S5/3436 ,  H01S2301/173 ,  H01S2304/04

摘要： In the S3-type semiconductor laser, when an angle of a first growth profile line to the first principal plane, the first growth profile line connecting respective lower side lines of an upper inclined plane and a lower inclined plane of the first layer of the first conduction type cladding layer is null1, an angle of a second growth profile line to the first principal plane, the second growth profile line connecting respective lower side lines of an upper inclined plane and a lower inclined plane of the second layer of the first conduction type cladding layer is null2, an angle of a third growth profile line to the first principal plane, the third growth profile line connecting respective lower side lines of an upper inclined plane and a lower inclined plane of the third layer of the first conduction type cladding layer is null3, and an angle of a fourth growth profile line to the first principal plane, the fourth growth profile line connecting respective lower side lines of an upper inclined plane and a lower inclined plane of the fourth layer of the first conduction type cladding layer is null4, relationships null1 null3, null3

公开(公告)号：US20020111034A1

公开(公告)日：2002-08-15

申请号：US10073877

申请日：2002-02-14

申请人： Fujitsu Quantum Devices Limited

发明人： Takayuki Watanabe ,  Tsutomu Michitsuta ,  Taro Hasegawa ,  Takuya Fujii

IPC分类号： H01L021/302 ,  H01L021/3205 ,  H01L021/00

CPC分类号： H01L21/30617 ,  H01S5/2081 ,  H01S5/2275 ,  H01S5/3235

摘要： A process of manufacturing a semiconductor device includes the steps of forming a stacked structure of a first III-V compound semiconductor layer containing In and having a composition different from InP and a second III-V compound semiconductor layer containing In. The second III-V compound semiconductor layer is formed over the first III-V compound semiconductor layer and growing an InP layer at regions adjacent the stacked structure to form a stepped structure of InP. The process further includes the step of wet-etching the stepped structure and the second III-V compound semiconductor layer using an etchant containing hydrochloric acid and acetic acid to remove at least the second III-V compound semiconductor layer.

摘要翻译： 制造半导体器件的方法包括以下步骤：形成包含In并且具有不同于InP的组成的第一III-V族化合物半导体层和包含In的第二III-V化合物半导体层的叠层结构。 在第一III-V族化合物半导体层上形成第二III-V族化合物半导体层，并在邻近堆叠结构的区域生长InP层，以形成InP的阶梯状结构。 该方法还包括使用含有盐酸和乙酸的蚀刻剂来湿式蚀刻阶梯结构和第二III-V化合物半导体层以去除至少第二III-V族化合物半导体层的步骤。