公开(公告)号：US5117489A

公开(公告)日：1992-05-26

申请号：US471684

申请日：1990-01-26

申请人： Shinji Komori ,  Hidehiro Takata ,  Toshiyuki Tamura ,  Fumiyasu Asai ,  Takeshi Fukuhara

发明人： Shinji Komori ,  Hidehiro Takata ,  Toshiyuki Tamura ,  Fumiyasu Asai ,  Takeshi Fukuhara

IPC分类号： G06F9/44

CPC分类号： G06F9/4436

摘要： A data-driven processor which has a packet assembling unit to add a tag information to the sequentially inputted data when the input data has no tag information, such as destination address or the like, thereby enabling the data to be inputted without using an external circuit, such as a host processor, and improving the data input rate and which also has a packet outputting and rearranging unit for rearranging an output packet stream in a predetermined order to thereby output the data information only, so that it is possible that the data is outputted without any external circuit, such as a host processor, the output rate is improved and the data output is executed in a predetermined order.

摘要翻译： 数据驱动处理器具有分组组合单元，用于当输入数据不具有诸如目的地址等的标签信息时，将标签信息添加到顺序输入的数据，从而使得能够在不使用外部电路的情况下输入数据 ，诸如主处理器，并且提高数据输入速率，并且还具有分组输出和重排单元，用于以预定顺序重新排列输出分组流，从而仅输出数据信息，使得数据可能是 在没有任何外部电路的情况下输出，例如主机处理器，输出速率得到改善，并且以预定顺序执行数据输出。

公开(公告)号：US5404553A

公开(公告)日：1995-04-04

申请号：US819164

申请日：1992-01-02

申请人： Shinji Komori ,  Hidehiro Takata ,  Toshiyuki Tamura ,  Fumiyasu Asai ,  Hirono Tsubota

发明人： Shinji Komori ,  Hidehiro Takata ,  Toshiyuki Tamura ,  Fumiyasu Asai ,  Hirono Tsubota

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/44 ,  G06F9/46 ,  G06F9/00

CPC分类号： G06F9/52 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3875 ,  G06F9/4436

摘要： A microprocessor which can execute a test and set instruction for an exclusive control by combination of a few simple instructions, and data flow microprocessor which realizes high operation performance mainly in vector operation by reading out of data to be operated, writing in operation result and executing memory access in short time period and in parallel, and whose running efficiency of program is high in multi-processor construction.

摘要翻译： 一种微处理器，其可以通过组合几个简单指令执行专用控制的测试和设置指令，以及主要在向量操作中实现高操作性能的数据流微处理器，通过读出要被操作的数据，写入操作结果和执行 内存访问在短时间内并行，并且程序的运行效率在多处理器构建中高。

公开(公告)号：US5392442A

公开(公告)日：1995-02-21

申请号：US837128

申请日：1992-02-19

申请人： Shinji Komori ,  Hidehiro Takata ,  Toshiyuki Tamura ,  Fumiyasu Asai ,  Takeshi Fukuhara

发明人： Shinji Komori ,  Hidehiro Takata ,  Toshiyuki Tamura ,  Fumiyasu Asai ,  Takeshi Fukuhara

IPC分类号： E04B1/41 ,  F16B13/08 ,  F16B13/14 ,  G06F9/06

CPC分类号： F16B13/0808 ,  Y10S411/908

摘要： A data-driven processor which has a packet assembling unit to add a tag information to the sequentially inputted data when the input data has no tag information, such as destination address or the like, thereby enabling the data to be inputted without using an external circuit, such as a host processor, and improving the data input rate and which also has a packet outputting and rearranging unit for rearranging an output packet stream in a predetermined order to thereby output the data information only, so that it is possible that the data is outputted without any external circuit, such as a host processor, the output rate is improved, and the data output is executed in a predetermined order.

摘要翻译： 数据驱动处理器具有分组组合单元，用于当输入数据不具有诸如目的地址等的标签信息时，将标签信息添加到顺序输入的数据，从而使得能够在不使用外部电路的情况下输入数据 ，诸如主处理器，并且提高数据输入速率，并且还具有分组输出和重排单元，用于以预定顺序重新排列输出分组流，从而仅输出数据信息，使得数据可能是 在没有任何外部电路的情况下输出，诸如主处理器，输出速率得到改善，并且以预定顺序执行数据输出。

公开(公告)号：US4882704A

公开(公告)日：1989-11-21

申请号：US157194

申请日：1988-02-17

申请人： Shinji Komori ,  Hidehiro Takata ,  Toshiyuki Tamura ,  Fumiyasu Asai

发明人： Shinji Komori ,  Hidehiro Takata ,  Toshiyuki Tamura ,  Fumiyasu Asai

IPC分类号： G06F13/42 ,  H04J3/04

CPC分类号： G06F7/00 ,  G06F13/4213 ,  H04J3/047 ,  G06F2207/3864

摘要： A hand-shake type control circuit for controlling a data transfer circuit according to the status of a data transfer request signal. The data transfer request signal is initially received at a NAND gate and is also directly coupled to the reset input of are set flip-flop. The output of the NAND gate is used as a first control signal to set the flip-flop and to cause another circuit to activate data transfer. The flip-flop output is a second control signal which is reset only when the transfer request signal changes from an active to an inactive status. The second control signal is coupled to an input of the NAND gate and inactivates the first control signal. Thus, data transfer cannot recur until after the data transfer request signal changes to an inactive status so that parasitic oscillations are eliminated. The flip-flop consists of two, two input NAND gates that are located out of the path of data transfer and that are easier to fabricate than the prior art D flip-flop.

摘要翻译： 一种用于根据数据传送请求信号的状态控制数据传送电路的握手型控制电路。 数据传送请求信号最初在NAND门处被接收并且也直接耦合到被设置的触发器的复位输入。 NAND门的输出用作第一控制信号以设置触发器并使另一电路激活数据传输。 触发器输出是仅在传送请求信号从活动状态变为非活动状态时才复位的第二控制信号。 第二控制信号耦合到NAND门的输入并使第一控制信号无效。 因此，在数据传输请求信号变为无效状态之后，数据传送不能重复，以便消除寄生振荡。 触发器由两个，两个输入NAND门组成，它们位于数据传输路径之外，并且比现有技术的D触发器更容易制造。

公开(公告)号：US5666535A

公开(公告)日：1997-09-09

申请号：US330880

申请日：1994-10-28

申请人： Shinji Komori ,  Hidehiro Takata ,  Toshiyuki Tamura ,  Fumiyasu Asai ,  Hirono Tsubota

发明人： Shinji Komori ,  Hidehiro Takata ,  Toshiyuki Tamura ,  Fumiyasu Asai ,  Hirono Tsubota

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/44 ,  G06F9/46 ,  G06F9/00

CPC分类号： G06F9/52 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3875 ,  G06F9/4436

摘要： A microprocessor which can execute a test and set instruction for an exclusive control by combination of a few simple instructions, and data flow microprocessor which realizes high operation performance mainly in vector operation by reading out of data to be operated, writing in operation result and executing memory access in short time period and in parallel, and whose running efficiency of program is high in multi-processor construction.

摘要翻译： 一种微处理器，其可以通过组合几个简单指令执行专用控制的测试和设置指令，以及主要在向量操作中实现高操作性能的数据流微处理器，通过读出要被操作的数据，写入操作结果和执行 内存访问在短时间内并行，并且程序的运行效率在多处理器构建中高。

公开(公告)号：US4980851A

公开(公告)日：1990-12-25

申请号：US284963

申请日：1988-12-15

申请人： Shinji Komori ,  Hidehiro Takata ,  Toshiyuki Tamura ,  Fumiyasu Asai ,  Tetsuo Yamasaki ,  Kenji Shima

发明人： Shinji Komori ,  Hidehiro Takata ,  Toshiyuki Tamura ,  Fumiyasu Asai ,  Tetsuo Yamasaki ,  Kenji Shima

IPC分类号： G06F13/38 ,  G06F5/08 ,  G06F13/42 ,  G11C7/00

CPC分类号： G06F13/4213 ,  Y02B60/1228 ,  Y02B60/1235

摘要： A pipelined processor is provided with a plurality of control stages controlling a datapath made up of a plurality of parallel static-type data latches. The latches each include a feedback circuit, typically a field-effect transistor, which is enabled by a data latch control signal from a particular control stage. Enabling the feedback stage consumes power. A data stagnation detection circuit detects a data stagnation in the datapath, by use of handshake control signals exchanged between the control stages. The data stagnation detection circuit inhibits enablement of the feedback circuit when no data stagnation is detected, reducing power used in the latch.

摘要翻译： 流水线处理器设置有多个控制级，控制由多个并行静态数据锁存器组成的数据路径。 锁存器各自包括反馈电路，通常是场效应晶体管，其通过来自特定控制级的数据锁存器控制信号使能。 启用反馈级消耗电力。 数据停滞检测电路通过使用在控制级之间交换的握手控制信号来检测数据通路中的数据停滞。 当没有检测到数据停滞时，数据停滞检测电路禁止反馈电路的使能，减少锁存器中使用的功率。

公开(公告)号：US5182799A

公开(公告)日：1993-01-26

申请号：US416887

申请日：1989-10-04

申请人： Toshiyuki Tamura ,  Masaki Fujita ,  Shinji Komori ,  Hisakazu Sato ,  Hidehiro Takata

发明人： Toshiyuki Tamura ,  Masaki Fujita ,  Shinji Komori ,  Hisakazu Sato ,  Hidehiro Takata

IPC分类号： G06F15/82 ,  G06F9/44 ,  G06F17/30

CPC分类号： G06F17/30949 ,  G06F9/4436

摘要： A data retrieving apparatus having an address generator for selecting partly at least one of bit strings of the identification data and generating a hashed address by a reversible operation thereof when a packet having an operand data and a plurality of identification data is inputted, a hash memory for being accessed by the hashed address, a match detector for comparing the identification data of the stored packet with the identification data of the inputted packet and judging match/mismatch thereof when a valid packet is already stored in the hashed address generated from the inputted packet, an associative memory unit for storing the identification data of the inputted packet as a retrieval data when the match detector judges to be mismatch, and judging match/mismatch of the identification data already stored with the identification data of the inputted packet when a packet is inputted, and an output selector for selecting an output from the hash memory or the associative memory unit in response to the result of judgement of said associative memory unit.

摘要翻译： 一种数据检索装置，具有地址发生器，用于当输入具有操作数据和多个识别数据的分组时，部分地选择识别数据的比特串中的一个以及通过其可逆操作产生散列的地址，哈希存储器 用于通过散列地址访问的匹配检测器，用于将存储的分组的识别数据与输入的分组的识别数据进行比较，并且当有效分组已经存储在从输入分组生成的散列地址中时，判断匹配/不匹配 相关联存储单元，用于当匹配检测器判断为不匹配时，将输入的分组的识别数据存储为检索数据，并且当分组是分组时，判断已经存储的识别数据与输入分组的识别数据的匹配/不匹配 以及用于选择来自散列存储器或关联存储器uni的输出的输出选择器 响应于所述关联存储器单元的判断结果。

公开(公告)号：US4953083A

公开(公告)日：1990-08-28

申请号：US373616

申请日：1989-06-28

申请人： Hidehiro Takata ,  Shinji Komori ,  Toshiyuki Tamura ,  Tetsuo Yamasaki ,  Kenji Shima

发明人： Hidehiro Takata ,  Shinji Komori ,  Toshiyuki Tamura ,  Tetsuo Yamasaki ,  Kenji Shima

IPC分类号： G06F9/44

CPC分类号： G06F9/4436

摘要： An improved data driven processor that utilizes queue buffers in the data path to maintain optimal dataflow.

摘要翻译： 改进的数据驱动处理器利用数据路径中的队列缓冲器来保持最佳数据流。

公开(公告)号：US5359720A

公开(公告)日：1994-10-25

申请号：US918489

申请日：1992-07-22

申请人： Toshiyuki Tamura ,  Masaki Fujita ,  Shinji Komori ,  Hisakazu Sato ,  Hidehiro Takata

发明人： Toshiyuki Tamura ,  Masaki Fujita ,  Shinji Komori ,  Hisakazu Sato ,  Hidehiro Takata

IPC分类号： G06F15/82 ,  G06F9/44 ,  G06F17/30 ,  G06F12/02

CPC分类号： G06F17/30949 ,  G06F9/4436

摘要： A data retrieving apparatus comprising an address an address generator for selecting partly at least one of bit strings of the identification data and generating a hashed address by a reversible operation thereof when a packet having an operand data and a plurality of identification data is inputted, a hash memory for being accessed by the hashed address, a match detector for comparing the identification data of the stored packet with the identification data of the inputted packet and judging match/mismatch thereof when a valid packet is already stored in the hashed address generated from the inputted packet, an associative memory unit for storing the identification data of the inputted packet as a retrieval data when the match detector judges to be mismatch, and judging match/mismatch of the identification data already stored with the identification data of the inputted packet when a packet is inputted, and an output selector for selecting an output from the hash memory or the associative memory unit in response to the result of judgment of said associative memory unit.

摘要翻译： 一种数据检索装置，包括地址生成器，用于当输入具有操作数据和多个识别数据的分组时，部分地选择识别数据的位串中的至少一个并通过其可逆操作产生散列地址， 哈希存储器，用于由散列地址访问;匹配检测器，用于将存储的分组的识别数据与输入的分组的识别数据进行比较，并且当有效分组已经存储在从 关联存储器单元，用于当匹配检测器判断为不匹配时，将所输入的分组的识别数据存储为检索数据;以及当a = 1时，已经存储的识别数据与输入的分组的识别数据的匹配/不匹配 输入分组，以及输出选择器，用于选择来自哈希存储器或协议的输出 响应于所述关联存储器单元的判断结果，存储单元。

公开(公告)号：US4992973A

公开(公告)日：1991-02-12

申请号：US217002

申请日：1988-07-08

申请人： Toshiyuki Tamura ,  Shinji Komori ,  Hidehiro Takata ,  Tetsuo Yamasaki ,  Hiroaki Terada ,  Katsuhiko Asada

发明人： Toshiyuki Tamura ,  Shinji Komori ,  Hidehiro Takata ,  Tetsuo Yamasaki ,  Hiroaki Terada ,  Katsuhiko Asada

IPC分类号： G06F5/08 ,  G06F13/38 ,  H04L1/24

CPC分类号： H04L1/24

摘要： A data transmission apparatus which is connected with a shift register of a plural stages forming a forward path of data transmission line, and a shift register of a plural stages forming a backward path of the same, and a loop-back part therebetween, and comprises bypasses between the shift register on the forward path and on the backward path to bypass the transmitted data when significant data does not exist on the loop-back part side from a stage on which the bypass is comprised and no data stays at a stage where the bypass is comprised, so that data is transmitted at high speed, and which is constructed to be able to control the bypass from external, so that testing of circuitry is easy.

摘要翻译： 一种数据传输装置，其与形成数据传输线的前向路径的多级的移位寄存器和形成其后向路径的多级的移位寄存器及其间的环回部分连接，并且包括 在来自包括旁路的级的环回部分侧上不存在有效数据时，在前向路径上的移位寄存器和反向路径之间绕过旁路传输数据，并且没有数据停留在 旁路被包括，使得数据以高速传输，并且被构造成能够从外部控制旁路，使得电路测试容易。