公开(公告)号：US07667317B2

公开(公告)日：2010-02-23

申请号：US11802888

申请日：2007-05-25

申请人： Fumiyuki Osanai ,  Atsushi Hiraishi ,  Toshio Sugano ,  Tsuyoshi Tomoyama ,  Satoshi Isa ,  Masahiro Yamaguchi ,  Masanori Shibamoto

发明人： Fumiyuki Osanai ,  Atsushi Hiraishi ,  Toshio Sugano ,  Tsuyoshi Tomoyama ,  Satoshi Isa ,  Masahiro Yamaguchi ,  Masanori Shibamoto

IPC分类号： H01L23/055

CPC分类号： H01L23/50 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/05599

摘要： A semiconductor package comprises a substrate, which has two surfaces and comprises first and second electrical paths. On one of the surfaces, a semiconductor chip is mounted. The semiconductor chip comprises a plurality of pads, which include a first pad to be supplied with a power supply and a second pad to be grounded. On the other surface, at least one bypass capacitor is mounted. The bypass capacitor comprises first and second terminals, which are connected to the first and the second pads through the first and the second electrical paths, respectively.

摘要翻译： 半导体封装包括具有两个表面并且包括第一和第二电路径的衬底。 在其中一个表面上安装了半导体芯片。 半导体芯片包括多个焊盘，其包括要供应电源的第一焊盘和要接地的第二焊盘。 在另一个表面上，安装至少一个旁路电容器。 旁路电容器包括分别通过第一和第二电路连接到第一和第二焊盘的第一和第二端子。

公开(公告)号：US20070273021A1

公开(公告)日：2007-11-29

申请号：US11802888

申请日：2007-05-25

申请人： Fumiyuki Osanai ,  Atsushi Hiraishi ,  Toshio Sugano ,  Tsuyoshi Tomoyama ,  Satoshi Isa ,  Masahiro Yamaguchi ,  Masanori Shibamoto

发明人： Fumiyuki Osanai ,  Atsushi Hiraishi ,  Toshio Sugano ,  Tsuyoshi Tomoyama ,  Satoshi Isa ,  Masahiro Yamaguchi ,  Masanori Shibamoto

IPC分类号： H01L23/12

CPC分类号： H01L23/50 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/05599

摘要： A semiconductor package comprises a substrate, which has two surfaces and comprises first and second electrical paths. On one of the surfaces, a semiconductor chip is mounted. The semiconductor chip comprises a plurality of pads, which include a first pad to be supplied with a power supply and a second pad to be grounded. On the other surface, at least one bypass capacitor is mounted. The bypass capacitor comprises first and second terminals, which are connected to the first and the second pads through the first and the second electrical paths, respectively.

摘要翻译： 半导体封装包括具有两个表面并且包括第一和第二电路径的衬底。 在其中一个表面上安装了半导体芯片。 半导体芯片包括多个焊盘，其包括要供应电源的第一焊盘和要接地的第二焊盘。 在另一个表面上，安装至少一个旁路电容器。 旁路电容器包括分别通过第一和第二电路连接到第一和第二焊盘的第一和第二端子。

公开(公告)号：US20060249842A1

公开(公告)日：2006-11-09

申请号：US11391449

申请日：2006-03-29

申请人： Satoshi Isa ,  Mitsuaki Katagiri ,  Fumiyuki Osanai

发明人： Satoshi Isa ,  Mitsuaki Katagiri ,  Fumiyuki Osanai

IPC分类号： H01L23/48

CPC分类号： H01L23/5286 ,  H01L23/3114 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device is disclosed including a data family pad layout wherein an effort is made to contrive layouts of a power lead wire and a ground lead wire to minimize effective inductance in priority to a length of a lead wire between a pad and a solder ball land of a semiconductor chip. Pad layouts are arrayed in two rows and one unit of the pad layout is configured such that a data power source and ground are adjacent to each other or one data is inserted between the data power source and the ground. Such configurations decrease mutual inductance between the data power sources and increase mutual inductance between the data power source and the ground causing reduction in effective inductance between the data power source and the ground with the resultant minimization of power and ground noises.

公开(公告)号：US07847377B2

公开(公告)日：2010-12-07

申请号：US11528688

申请日：2006-09-28

申请人： Fumiyuki Osanai ,  Mitsuaki Katagiri ,  Satoshi Isa

发明人： Fumiyuki Osanai ,  Mitsuaki Katagiri ,  Satoshi Isa

IPC分类号： H01L27/07

CPC分类号： H01L23/50 ,  H01L23/49838 ,  H01L23/4985 ,  H01L24/06 ,  H01L2224/05554

摘要： A semiconductor device includes a semiconductor chip having at a center area thereof first and second pad rows which include a plurality of first pads and a plurality of second pads, respectively. A package substrate is bonded to the semiconductor chip. The package substrate includes a substrate opening corresponding to a region including the first and second pad rows, first and second wiring positioned at opposite sides of the substrate opening, respectively, and a ball land disposed in the first wiring area. A bridge section is provided over the substrate opening to mutually connect the first and second wiring areas. The ball land is electrically connected to at least one of the second pads through the bridge section by a lead.

摘要翻译： 半导体器件包括半导体芯片，其半导体芯片在其中心区域具有分别包括多个第一焊盘和多个第二焊盘的第一焊盘行和第二焊盘行。 封装基板结合到半导体芯片。 封装基板包括对应于包括第一和第二焊盘列的区域的基板开口，分别位于基板开口的相对侧的第一和第二布线以及设置在第一布线区域中的球形区域。 桥接部分设置在基板开口上方以相互连接第一和第二布线区域。 球面通过导线通过桥接部分电连接到第二焊盘中的至少一个。

公开(公告)号：US07391113B2

公开(公告)日：2008-06-24

申请号：US11391449

申请日：2006-03-29

申请人： Satoshi Isa ,  Mitsuaki Katagiri ,  Fumiyuki Osanai

发明人： Satoshi Isa ,  Mitsuaki Katagiri ,  Fumiyuki Osanai

IPC分类号： H01L23/48

CPC分类号： H01L23/5286 ,  H01L23/3114 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device is disclosed including a data family pad layout wherein an effort is made to contrive layouts of a power lead wire and a ground lead wire to minimize effective inductance in priority to a length of a lead wire between a pad and a solder ball land of a semiconductor chip. Pad layouts are arrayed in two rows and one unit of the pad layout is configured such that a data power source and ground are adjacent to each other or one data is inserted between the data power source and the ground. Such configurations decrease mutual inductance between the data power sources and increase mutual inductance between the data power source and the ground causing reduction in effective inductance between the data power source and the ground with the resultant minimization of power and ground noises.

摘要翻译： 公开了一种半导体器件，其包括数据族焊盘布局，其中努力设计电源引线和接地引线的布局，以将焊盘和焊球焊盘之间的引线的长度优先于最小化有效电感 的半导体芯片。 焊盘布局排列成两行，并且焊盘布局的一个单位被配置为使得数据电源和接地彼此相邻或者在数据电源和地之间插入一个数据。 这样的配置减少数据电源之间的互感，并增加数据电源和地之间的互感，从而导致数据电源与地之间的有效电感的降低，从而导致功率和接地噪声的最小化。

公开(公告)号：US20070075440A1

公开(公告)日：2007-04-05

申请号：US11528688

申请日：2006-09-28

申请人： Fumiyuki Osanai ,  Mitsuaki Katagiri ,  Satoshi Isa

发明人： Fumiyuki Osanai ,  Mitsuaki Katagiri ,  Satoshi Isa

IPC分类号： H01L23/48

CPC分类号： H01L23/50 ,  H01L23/49838 ,  H01L23/4985 ,  H01L24/06 ,  H01L2224/05554

摘要： A semiconductor device includes a semiconductor chip having at a center area thereof first and second pad rows which include a plurality of first pads and a plurality of second pads, respectively. A package substrate is bonded to the semiconductor chip. The package substrate includes a substrate opening corresponding to a region including the first and second pad rows, first and second wiring positioned at opposite sides of the substrate opening, respectively, and a ball land disposed in the first wiring area. A bridge section is provided over the substrate opening to mutually connect the first and second wiring areas. The ball land is electrically connected to at least one of the second pads through the bridge section by a lead.

摘要翻译： 半导体器件包括半导体芯片，其半导体芯片在其中心区域具有分别包括多个第一焊盘和多个第二焊盘的第一焊盘行和第二焊盘行。 封装基板结合到半导体芯片。 封装基板包括对应于包括第一和第二焊盘列的区域的基板开口，分别位于基板开口的相对侧的第一和第二布线以及设置在第一布线区域中的球形区域。 桥接部分设置在基板开口上方以相互连接第一和第二布线区域。 球面通过导线通过桥接部分电连接到第二焊盘中的至少一个。

公开(公告)号：US07538431B2

公开(公告)日：2009-05-26

申请号：US12126681

申请日：2008-05-23

申请人： Satoshi Isa ,  Mitsuaki Katagiri ,  Fumiyuki Osanai

发明人： Satoshi Isa ,  Mitsuaki Katagiri ,  Fumiyuki Osanai

IPC分类号： H01L23/48

CPC分类号： H01L23/5286 ,  H01L23/3114 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device is disclosed including a data family pad layout wherein an effort is made to contrive layouts of a power lead wire and a ground lead wire to minimize effective inductance in priority to a length of a lead wire between a pad and a solder ball land of a semiconductor chip. Pad layouts are arrayed in two rows and one unit of the pad layout is configured such that a data power source and ground are adjacent to each other or one data is inserted between the data power source and the ground. Such configurations decrease mutual inductance between the data power sources and increase mutual inductance between the data power source and the ground causing reduction in effective inductance between the data power source and the ground with the resultant minimization of power and ground noises.

摘要翻译： 公开了一种半导体器件，其包括数据族焊盘布局，其中努力设计电源引线和接地引线的布局，以将焊盘和焊球焊盘之间的引线的长度优先于最小化有效电感 的半导体芯片。 焊盘布局排列成两行，并且焊盘布局的一个单位被配置为使得数据电源和接地彼此相邻或者在数据电源和地之间插入一个数据。 这样的配置减少数据电源之间的互感，并增加数据电源和地之间的互感，从而导致数据电源与地之间的有效电感的降低，从而导致功率和接地噪声的最小化。

公开(公告)号：US20070164435A1

公开(公告)日：2007-07-19

申请号：US11613914

申请日：2006-12-20

申请人： Kazutaka Koshiishi ,  Mitsuaki Katagiri ,  Satoshi Isa ,  Fumiyuki Osanai

发明人： Kazutaka Koshiishi ,  Mitsuaki Katagiri ,  Satoshi Isa ,  Fumiyuki Osanai

IPC分类号： H01L23/52

CPC分类号： H01L23/66 ,  H01L23/49822 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/19051 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0216 ,  H05K1/024 ,  H05K3/4688 ,  H05K2201/09309 ,  H01L2924/00

摘要： To reduce noise between a power supply wiring and ground wiring especially in a small, high-density semiconductor device for high-speed operation. A semiconductor device having a second dielectric layer 5 made of dielectric material of which the dielectric loss tan 6 is at least 0.2 and interposed between a power supply wiring layer 6 electrically connected to a semiconductor chip and a ground wiring layer 4, so composed that a dielectric loss generated in the second dielectric layer 5 acts as a low pass filter of the power supply wiring layer 6, and having a first dielectric layer 3 made of dielectric material whose dielectric loss is less than the dielectric loss tan 6 of the second dielectric layer 5 and interposed between a signal wiring layer 2 electrically connected to the semiconductor chip and the ground wiring layer 4.

摘要翻译： 为了降低电源布线和接地布线之间的噪音，特别是在高速运行的小型，高密度半导体器件中。 一种半导体器件，具有由绝缘材料制成的介电损耗tanδ为0.2以上且介于与半导体芯片电连接的电源布线层6和接地布线层4之间的第二介质层5， 在第二电介质层5中产生的介电损耗用作电源布线层6的低通滤波器，并且具有由介电损耗小于第二介电层的介电损耗tanδ的电介质材料制成的第一电介质层3 插入在与半导体芯片电连接的信号布线层2和接地布线层4之间。

公开(公告)号：US07569428B2

公开(公告)日：2009-08-04

申请号：US11525952

申请日：2006-09-25

申请人： Satoshi Isa ,  Satoshi Itaya ,  Mitsuaki Katagiri ,  Fumiyuki Osanai ,  Hiroki Fujisawa

发明人： Satoshi Isa ,  Satoshi Itaya ,  Mitsuaki Katagiri ,  Fumiyuki Osanai ,  Hiroki Fujisawa

IPC分类号： H01L21/82 ,  H01L23/52

CPC分类号： H01L23/50 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a method for manufacturing a method for manufacturing a semiconductor device which comprises a substrate, a semiconductor chip and a plurality of terminals. The method comprises preparing the substrate comprising an insulator which is formed with a plurality of signal lines, a plurality of power lines related to the plurality of signal lines and a plurality of ground lines related to the plurality of signal lines on the insulator in accordance with a predetermined layout. Each of the plurality of line groups comprises one of the power lines, one of the ground lines and one of the signal lines arranged between the one of the power lines and the one of the ground lines. Each of the plurality of line groups shares any one of the power line and the ground line with a neighboring line group of the plurality of line groups.

摘要翻译： 公开了一种制造半导体器件的方法的方法，该半导体器件包括衬底，半导体芯片和多个端子。 该方法包括制备包括绝缘体的衬底，所述绝缘体形成有多条信号线，与多条信号线相关的多条电力线以及与该绝缘体上的多条信号线相关的多条地线，根据 预定的布局。 多个线路组中的每一个包括电力线中的一条，接地线中的一条和布置在一条电力线和一条接地线之间的一条信号线。 所述多个线路组中的每一个与所述多个线路组中的相邻线路组共享所述电力线和接地线中的任何一个。

公开(公告)号：US20070069362A1

公开(公告)日：2007-03-29

申请号：US11525952

申请日：2006-09-25

申请人： Satoshi Isa ,  Satoshi Itaya ,  Mitsuaki Katagiri ,  Fumiyuki Osanai ,  Hiroki Fujisawa

发明人： Satoshi Isa ,  Satoshi Itaya ,  Mitsuaki Katagiri ,  Fumiyuki Osanai ,  Hiroki Fujisawa

IPC分类号： H01L23/48

CPC分类号： H01L23/50 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a method for manufacturing a method for manufacturing a semiconductor device which comprises a substrate, a semiconductor chip and a plurality of terminals. The method comprises preparing the substrate comprising an insulator which is formed with a plurality of signal lines, a plurality of power lines related to the plurality of signal lines and a plurality of ground lines related to the plurality of signal lines on the insulator in accordance with a predetermined layout. Each of the plurality of line groups comprises one of the power lines, one of the ground lines and one of the signal lines arranged between the one of the power lines and the one of the ground lines. Each of the plurality of line groups shares any one of the power line and the ground line with a neighboring line group of the plurality of line groups.

摘要翻译： 公开了一种制造半导体器件的方法的方法，该半导体器件包括衬底，半导体芯片和多个端子。 该方法包括制备包括绝缘体的衬底，所述绝缘体形成有多条信号线，与多条信号线相关的多条电力线以及与该绝缘体上的多条信号线相关的多条地线，根据 预定的布局。 多个线路组中的每一个包括电力线中的一条，接地线中的一条和布置在一条电力线和一条接地线之间的一条信号线。 所述多个线路组中的每一个与所述多个线路组中的相邻线路组共享所述电力线和接地线中的任何一个。