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1.发明授权Method for manufacturing semiconductor device, semiconductor device and apparatus comprising same 有权制造半导体器件的方法，半导体器件及包括该器件的器件公开(公告)号：US07569428B2
公开(公告)日：2009-08-04
申请号：US11525952
申请日：2006-09-25
CPC分类号： H01L23/50 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method for manufacturing a method for manufacturing a semiconductor device which comprises a substrate, a semiconductor chip and a plurality of terminals. The method comprises preparing the substrate comprising an insulator which is formed with a plurality of signal lines, a plurality of power lines related to the plurality of signal lines and a plurality of ground lines related to the plurality of signal lines on the insulator in accordance with a predetermined layout. Each of the plurality of line groups comprises one of the power lines, one of the ground lines and one of the signal lines arranged between the one of the power lines and the one of the ground lines. Each of the plurality of line groups shares any one of the power line and the ground line with a neighboring line group of the plurality of line groups.
摘要翻译： 公开了一种制造半导体器件的方法的方法，该半导体器件包括衬底，半导体芯片和多个端子。 该方法包括制备包括绝缘体的衬底，所述绝缘体形成有多条信号线，与多条信号线相关的多条电力线以及与该绝缘体上的多条信号线相关的多条地线，根据 预定的布局。 多个线路组中的每一个包括电力线中的一条，接地线中的一条和布置在一条电力线和一条接地线之间的一条信号线。 所述多个线路组中的每一个与所述多个线路组中的相邻线路组共享所述电力线和接地线中的任何一个。
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2.发明申请Method for manufacturing semiconductor device, semiconductor device and apparatus comprising same 有权制造半导体器件的方法，半导体器件及包括该器件的器件公开(公告)号：US20070069362A1
公开(公告)日：2007-03-29
申请号：US11525952
申请日：2006-09-25
IPC分类号： H01L23/48
CPC分类号： H01L23/50 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method for manufacturing a method for manufacturing a semiconductor device which comprises a substrate, a semiconductor chip and a plurality of terminals. The method comprises preparing the substrate comprising an insulator which is formed with a plurality of signal lines, a plurality of power lines related to the plurality of signal lines and a plurality of ground lines related to the plurality of signal lines on the insulator in accordance with a predetermined layout. Each of the plurality of line groups comprises one of the power lines, one of the ground lines and one of the signal lines arranged between the one of the power lines and the one of the ground lines. Each of the plurality of line groups shares any one of the power line and the ground line with a neighboring line group of the plurality of line groups.
摘要翻译： 公开了一种制造半导体器件的方法的方法，该半导体器件包括衬底，半导体芯片和多个端子。 该方法包括制备包括绝缘体的衬底，所述绝缘体形成有多条信号线，与多条信号线相关的多条电力线以及与该绝缘体上的多条信号线相关的多条地线，根据 预定的布局。 多个线路组中的每一个包括电力线中的一条，接地线中的一条和布置在一条电力线和一条接地线之间的一条信号线。 所述多个线路组中的每一个与所述多个线路组中的相邻线路组共享所述电力线和接地线中的任何一个。
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公开(公告)号：US20060249842A1
公开(公告)日：2006-11-09
申请号：US11391449
申请日：2006-03-29
申请人： Satoshi Isa , Mitsuaki Katagiri , Fumiyuki Osanai
发明人： Satoshi Isa , Mitsuaki Katagiri , Fumiyuki Osanai
IPC分类号： H01L23/48
CPC分类号： H01L23/5286 , H01L23/3114 , H01L23/50 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device is disclosed including a data family pad layout wherein an effort is made to contrive layouts of a power lead wire and a ground lead wire to minimize effective inductance in priority to a length of a lead wire between a pad and a solder ball land of a semiconductor chip. Pad layouts are arrayed in two rows and one unit of the pad layout is configured such that a data power source and ground are adjacent to each other or one data is inserted between the data power source and the ground. Such configurations decrease mutual inductance between the data power sources and increase mutual inductance between the data power source and the ground causing reduction in effective inductance between the data power source and the ground with the resultant minimization of power and ground noises.
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公开(公告)号：US07847377B2
公开(公告)日：2010-12-07
申请号：US11528688
申请日：2006-09-28
申请人： Fumiyuki Osanai , Mitsuaki Katagiri , Satoshi Isa
发明人： Fumiyuki Osanai , Mitsuaki Katagiri , Satoshi Isa
IPC分类号： H01L27/07
CPC分类号： H01L23/50 , H01L23/49838 , H01L23/4985 , H01L24/06 , H01L2224/05554
摘要： A semiconductor device includes a semiconductor chip having at a center area thereof first and second pad rows which include a plurality of first pads and a plurality of second pads, respectively. A package substrate is bonded to the semiconductor chip. The package substrate includes a substrate opening corresponding to a region including the first and second pad rows, first and second wiring positioned at opposite sides of the substrate opening, respectively, and a ball land disposed in the first wiring area. A bridge section is provided over the substrate opening to mutually connect the first and second wiring areas. The ball land is electrically connected to at least one of the second pads through the bridge section by a lead.
摘要翻译： 半导体器件包括半导体芯片，其半导体芯片在其中心区域具有分别包括多个第一焊盘和多个第二焊盘的第一焊盘行和第二焊盘行。 封装基板结合到半导体芯片。 封装基板包括对应于包括第一和第二焊盘列的区域的基板开口，分别位于基板开口的相对侧的第一和第二布线以及设置在第一布线区域中的球形区域。 桥接部分设置在基板开口上方以相互连接第一和第二布线区域。 球面通过导线通过桥接部分电连接到第二焊盘中的至少一个。
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公开(公告)号：US07391113B2
公开(公告)日：2008-06-24
申请号：US11391449
申请日：2006-03-29
申请人： Satoshi Isa , Mitsuaki Katagiri , Fumiyuki Osanai
发明人： Satoshi Isa , Mitsuaki Katagiri , Fumiyuki Osanai
IPC分类号： H01L23/48
CPC分类号： H01L23/5286 , H01L23/3114 , H01L23/50 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device is disclosed including a data family pad layout wherein an effort is made to contrive layouts of a power lead wire and a ground lead wire to minimize effective inductance in priority to a length of a lead wire between a pad and a solder ball land of a semiconductor chip. Pad layouts are arrayed in two rows and one unit of the pad layout is configured such that a data power source and ground are adjacent to each other or one data is inserted between the data power source and the ground. Such configurations decrease mutual inductance between the data power sources and increase mutual inductance between the data power source and the ground causing reduction in effective inductance between the data power source and the ground with the resultant minimization of power and ground noises.
摘要翻译： 公开了一种半导体器件，其包括数据族焊盘布局，其中努力设计电源引线和接地引线的布局，以将焊盘和焊球焊盘之间的引线的长度优先于最小化有效电感 的半导体芯片。 焊盘布局排列成两行，并且焊盘布局的一个单位被配置为使得数据电源和接地彼此相邻或者在数据电源和地之间插入一个数据。 这样的配置减少数据电源之间的互感，并增加数据电源和地之间的互感，从而导致数据电源与地之间的有效电感的降低，从而导致功率和接地噪声的最小化。
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公开(公告)号：US20070075440A1
公开(公告)日：2007-04-05
申请号：US11528688
申请日：2006-09-28
申请人： Fumiyuki Osanai , Mitsuaki Katagiri , Satoshi Isa
发明人： Fumiyuki Osanai , Mitsuaki Katagiri , Satoshi Isa
IPC分类号： H01L23/48
CPC分类号： H01L23/50 , H01L23/49838 , H01L23/4985 , H01L24/06 , H01L2224/05554
摘要： A semiconductor device includes a semiconductor chip having at a center area thereof first and second pad rows which include a plurality of first pads and a plurality of second pads, respectively. A package substrate is bonded to the semiconductor chip. The package substrate includes a substrate opening corresponding to a region including the first and second pad rows, first and second wiring positioned at opposite sides of the substrate opening, respectively, and a ball land disposed in the first wiring area. A bridge section is provided over the substrate opening to mutually connect the first and second wiring areas. The ball land is electrically connected to at least one of the second pads through the bridge section by a lead.
摘要翻译： 半导体器件包括半导体芯片，其半导体芯片在其中心区域具有分别包括多个第一焊盘和多个第二焊盘的第一焊盘行和第二焊盘行。 封装基板结合到半导体芯片。 封装基板包括对应于包括第一和第二焊盘列的区域的基板开口，分别位于基板开口的相对侧的第一和第二布线以及设置在第一布线区域中的球形区域。 桥接部分设置在基板开口上方以相互连接第一和第二布线区域。 球面通过导线通过桥接部分电连接到第二焊盘中的至少一个。
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公开(公告)号：US07538431B2
公开(公告)日：2009-05-26
申请号：US12126681
申请日：2008-05-23
申请人： Satoshi Isa , Mitsuaki Katagiri , Fumiyuki Osanai
发明人： Satoshi Isa , Mitsuaki Katagiri , Fumiyuki Osanai
IPC分类号： H01L23/48
CPC分类号： H01L23/5286 , H01L23/3114 , H01L23/50 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device is disclosed including a data family pad layout wherein an effort is made to contrive layouts of a power lead wire and a ground lead wire to minimize effective inductance in priority to a length of a lead wire between a pad and a solder ball land of a semiconductor chip. Pad layouts are arrayed in two rows and one unit of the pad layout is configured such that a data power source and ground are adjacent to each other or one data is inserted between the data power source and the ground. Such configurations decrease mutual inductance between the data power sources and increase mutual inductance between the data power source and the ground causing reduction in effective inductance between the data power source and the ground with the resultant minimization of power and ground noises.
摘要翻译： 公开了一种半导体器件，其包括数据族焊盘布局，其中努力设计电源引线和接地引线的布局，以将焊盘和焊球焊盘之间的引线的长度优先于最小化有效电感 的半导体芯片。 焊盘布局排列成两行，并且焊盘布局的一个单位被配置为使得数据电源和接地彼此相邻或者在数据电源和地之间插入一个数据。 这样的配置减少数据电源之间的互感，并增加数据电源和地之间的互感，从而导致数据电源与地之间的有效电感的降低，从而导致功率和接地噪声的最小化。
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公开(公告)号：US20070164435A1
公开(公告)日：2007-07-19
申请号：US11613914
申请日：2006-12-20
IPC分类号： H01L23/52
CPC分类号： H01L23/66 , H01L23/49822 , H01L2224/48227 , H01L2224/49175 , H01L2924/19051 , H01L2924/3011 , H01L2924/3025 , H05K1/0216 , H05K1/024 , H05K3/4688 , H05K2201/09309 , H01L2924/00
摘要： To reduce noise between a power supply wiring and ground wiring especially in a small, high-density semiconductor device for high-speed operation. A semiconductor device having a second dielectric layer 5 made of dielectric material of which the dielectric loss tan 6 is at least 0.2 and interposed between a power supply wiring layer 6 electrically connected to a semiconductor chip and a ground wiring layer 4, so composed that a dielectric loss generated in the second dielectric layer 5 acts as a low pass filter of the power supply wiring layer 6, and having a first dielectric layer 3 made of dielectric material whose dielectric loss is less than the dielectric loss tan 6 of the second dielectric layer 5 and interposed between a signal wiring layer 2 electrically connected to the semiconductor chip and the ground wiring layer 4.
摘要翻译： 为了降低电源布线和接地布线之间的噪音，特别是在高速运行的小型，高密度半导体器件中。 一种半导体器件，具有由绝缘材料制成的介电损耗tanδ为0.2以上且介于与半导体芯片电连接的电源布线层6和接地布线层4之间的第二介质层5， 在第二电介质层5中产生的介电损耗用作电源布线层6的低通滤波器，并且具有由介电损耗小于第二介电层的介电损耗tanδ的电介质材料制成的第一电介质层3 插入在与半导体芯片电连接的信号布线层2和接地布线层4之间。
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9.发明授权公开(公告)号：US07694245B2
公开(公告)日：2010-04-06
申请号：US11710965
申请日：2007-02-27
申请人： Mitsuaki Katagiri , Satoshi Nakamura , Takashi Suga , Yoji Nishio , Satoshi Isa , Satoshi Itaya
发明人： Mitsuaki Katagiri , Satoshi Nakamura , Takashi Suga , Yoji Nishio , Satoshi Isa , Satoshi Itaya
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L23/50 , H01L2224/05554 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/49175 , H01L2224/73265 , H01L2924/15311 , H01L2924/181 , H01L2924/3011 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A method for designing a semiconductor package is disclosed, wherein the semiconductor package comprises a semiconductor chip and an adjustment target. A first target variable is calculated in consideration of a first transition state where an output level of the semiconductor chip changes from a low level to a high level. A second target variable is calculated in consideration of a second transition state where an output level of the semiconductor chip changes from the high level to the low level. Inferior one of the first and the second target variables is selected as a main target variable. The main target variable and a predetermined constraint represented in frequency domain are compared to decide design guidelines for the adjustment target.
摘要翻译： 公开了一种用于设计半导体封装的方法，其中半导体封装包括半导体芯片和调整对象。 考虑到半导体芯片的输出电平从低电平变为高电平的第一转变状态来计算第一目标变量。 考虑到半导体芯片的输出电平从高电平变为低电平的第二过渡状态来计算第二目标变量。 选择第一和第二目标变量之一作为主要目标变量。 比较主要目标变量和在频域中表示的预定约束，以决定调整目标的设计指南。
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公开(公告)号：US08243465B2
公开(公告)日：2012-08-14
申请号：US12707996
申请日：2010-02-18
申请人： Satoshi Itaya , Satoshi Isa , Mitsuaki Katagiri , Dai Sasaki
发明人： Satoshi Itaya , Satoshi Isa , Mitsuaki Katagiri , Dai Sasaki
CPC分类号： H05K1/181 , G11C5/063 , H01L23/49816 , H01L23/49827 , H01L23/50 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0657 , H01L25/18 , H01L2224/05554 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/48247 , H01L2224/49175 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2924/00014 , H01L2924/0102 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device reduces the impedance of a wiring for supplying the circuit excluding a data output circuit with a power source voltage or a ground voltage and of speedup of data signal transmission in the data output circuit. Additional substrates 2a, 2b are on the upper surface of semiconductor chip 1. First additional wiring layer for power source 10d and first additional wiring layer for ground 10s formed on respective additional substrates 2a, 2b form prescribed conductive areas on semiconductor chip 1. First power source wiring 40C1d or first ground wiring 40C1s are interconnected through additional wiring layers 10d and 10s. Second power source wiring 40C2d and second ground wiring 40C2s, which is extended in the same direction as with DQ system signal wiring 40CDQ, forms a feedback current path. Second power source wiring 40C2d and second ground wiring 40C2s are disposed adjacent to DQ system signal wiring 40CDQ.
摘要翻译： 在数据输出电路中，半导体器件减少了用于提供具有电源电压或接地电压以及数据信号传输加速的数据输出电路的电路的布线的阻抗。 附加的基板2a，2b位于半导体芯片1的上表面上。形成在各个附加基板2a，2b上的用于电源10d的第一附加布线层和用于接地的第一附加布线层10形成半导体芯片1上规定的导电区域。 源极配线40C1d或第一接地配线40C1通过附加配线层10d和10s相互连接。 与DQ系统信号线40CDQ相同的方向延伸的第二电源配线40C2d和第二接地配线40C2s形成反馈电流路径。 第二电源配线40C2d和第二接地配线40C2s配置在与DQ系统信号配线40CDQ相邻的位置。
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